floresta:
Regardless of how the LCD controller interprets what is happening the program code should be issuing what is essentially three initial 'function set' commands. Don't forget that the 4-bit mode was not originally intended to 'save' I/O pins, it was designed to interface with 4-bit microprocessors such as the Intel 4004.My opinion is that, since there is no documentation as to what is actually going on inside the controller, we should not try to figure out what each of the individual steps may or may not be doing.
I think we should conceptually group the first three 'function set' instructions together and describe what they are doing as a whole and that is to get the controller into a known state.
While the first the 3 humps of E do get the LCD to a known state of 8 bit mode, it isn't always 3 actual function set commands.
The LCD may process it as 3 commands or 2, it depends on the mode the LCD is currently in.
We don't have to know exactly what is going on inside the chip.
All we have to know is the documented commands. And based on that, we can know that the 3 humps of E in that sequence will generate either 3 or 2 actual commands to the LCD. And that in order to cover the case where the LCD is out of nibble sync, the fist hump of E can generate a command that could be almost anything including a home instruction (when processing that first "function set command", the LCD sees it as the 2nd/lower nibble of the instruction and that nibble will have bits 0 and 1 set. So if the first nibble sent prior to the initialization sequence was a zero, the LCD will process a home instruction), and that is why the first delay in that sequence is so much longer than the other delays.
It must accommodate that worst case command execution time (home instruction) since busy can't yet be used.
The initialization tables in figures 23 & 24 have assumed a 100kHz clock which explains why the initial delay is 4.1ms (vs 1.52ms from table 6) and the other delay(s) is 100us (vs 37us from table 6)
Those delays are exactly 2.7x the delays in table 6 for clear/home of 1.52ms and 37us for other instructions.
Nothing magic, the initialization sequence chart uses normal commands but appears to have used a slower reference of 100khz instead of the 270kHz that was used in table 6.
--- bill