ADC convertion problems when changing ADC clock prescaler

Projects Programming
1

Hello all,

I'm trying to change ADC clock prescaler for the need of a higher sampling rate, but I find the convertion results changed when changing the clock. For example, when the prescaler is default (clk/128), the convertion results for a 2.5V DC power supply is 2.50V, when the perscaler is 16 (clk/16) the results for the same signal varies between 2.38V and 2.48V, when the clock is clk/2, the result is 1.40V, as if there is an offset.

I use the following codes in void setup() to change the clock:

    bitClear(ADCSRA,ADPS0);
    bitClear(ADCSRA,ADPS1);
    bitSet(ADCSRA,ADPS2);

And I use analogRead() in loop to read the signal.

I'm using Arduino Mega 2560, and I changed nothing else except for ADC clock. So far I haven't figured out what happened. Does anybody have some ideas?

2

A little outside my knowlege but I suspect that the important part of the datasheet is

By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be as high as 1000kHz to get a higher sample rate.

At higher sampling rates, the processor can't do a full conversion and the result will not be a 10-bit result. Try shifting the result two positions (8 bit)

// read A0
int val = analogRead(A0);
// 8 bit resolution
val /= 4;
Serial.println(val);
3

1. This is a 10-bit ADC. So, there is a need of 10 clock pulses to convert the sample of an analog voltage using SAR type ADC.

2. The recommended conversion clock frequency (clkADC) is: 50 kHz to 200 kHz and the optimum frequency is: 125 kHz. Thus, the conversion time is: 200 us (1/50000*10) to 50 us; optimum is: 80 us at 125 kHz. If we operate the ADC outside the given range of clkADC, the result is not guaranteed. Why? It is because the electronics takes sometime to respond to clkADC; also, the characteristic of the hold circuit (the capacitor) is a matter concern.

3. When the ADC is operated at clkADC less than 50 kHz, the hold circuit starts to loose the sampled value (the input signal) through leakage path. It is because, the clkADC is slow. The transition of the SAR from 1-bit to the next upper bit is taking too long time during which the hold circuit starts to loose sampled value. The sampled value of the input signal must remain stable/undisturbed until the conversion is complete.

4. When the ADC is operated at clkADC greater than 200 kHz, the SAR fails to respond to the clkADC pulses; as a result, the output value could not be updated properly.

4

Thank you for the explanation! Seems that ADC won't perform very well at a very high clock. It's not the problem of resolution.