When there is a reset on the classic AVR chips, the watchdog timer will stay on if either the relevant fuse is set, OR if the watchdog had caused the reset. But the Control register is zeroed, which causes the timeout period to be the minimum possible (about 16ms) If you don't do something else to the watchdog (disable it or change the timeout), the system will be reset again in 16ms.
This is the cause of the "boot loop" with the old ATmegaboot bootloader - if an application enables the watchdog and a WDT occurs, the chip resets, entering the bootloader. The bootloader does nothing with the watchdog, and then prepares to wait ~10s for possible upload commands on the serial port. 16ms into the wait, the watchdog resets the chip again, and this repeats, over and over again. (Even if there ARE upload commands "immediately", it will still take longer than 16ms to upload a sketch, so ... bootloader loop.)