Clock speed logic

Exactly, Magician. The compiler unrolled the loop and did straight bit banging. It put a 3 in one register and a 0 in the zero register and alternated the out instructions. Once I use 4 for del, it put them in a loop with an adiw, a cpi, a cpc, and a brne instruction. Much slower.

I think there is a way to set the timer2 up in fastPWM mode with a prescaler of 1. Couldn't you get 1 clock high and 1 clock low out of that?