Data Synchronization Barrier on R4 boards

Official Hardware Nano Family Nano R4
1

Hello everyone, I’m playing with the new nano R4 board and I have a doubt about the use of Data Synchronization Barrier of the Arm Cortex-M4 processor … If I want to blink RGB leds with direct register operations:

LEDR (P409) LEDG (P411) LEDB (P410) Color
0 1 1 Red
1 0 1 Green
1 1 0 Blue

It is enough using __DSB() or asm volatile("dsb") only one time inside the setup function like this:

#define PORTBASE 0x40040000 /* Port Base */

#define P400PFS 0x0900  // Port 4 Pin Function Select Register
#define PFS_P409PFS ((volatile unsigned int *)(PORTBASE + P400PFS + ( 9 * 4))) // LEDR
#define PFS_P410PFS ((volatile unsigned int *)(PORTBASE + P400PFS + (10 * 4))) // LEDB
#define PFS_P411PFS ((volatile unsigned int *)(PORTBASE + P400PFS + (11 * 4))) // LEDG

#define PFS_P409PFS_BY ((volatile unsigned char  *)(PORTBASE + 0x0903 + (9 * 4))) // LEDR
#define PFS_P410PFS_BY ((volatile unsigned char  *)(PORTBASE + 0x0903 + (10 * 4))) // LEDB
#define PFS_P411PFS_BY ((volatile unsigned char  *)(PORTBASE + 0x0903 + (11 * 4))) // LEDG

void setup() {
 __DSB(); 
}

void loop() {
  // blink RED led
  *PFS_P409PFS_BY = 0x04;
  delay(1000);
  *PFS_P409PFS_BY = 0x05;
  delay(1000);
}

Or I need to call __DSB() instruction also inside the loop function?

2

If you remove the DSB thingy all together what do you see?

I don’t think you need it at all, if my memory serves me well, the Cortex-M4 memory model defines peripheral regions as strongly ordered, which ensures that register writes occur in the correct sequence without requiring extra barriers.

A DSB is needed after changing MPU settings or system control registers to ensure the core sees the new configuration before continuing.

3

Thanks for the reply J-M-L ! I was supposed to use data synchronization barrier when I write only 8bit (*PFS_P409PFS_BY = 0x04) instead whole 32bit (*PFS_P409PFS = 0x00000004) PFS register.

But looking better examples of @susan-parker (here the examples), she uses data synchronization barrier only for NVIC registers, not for PFS registers.

4

It is important to make absolutely sure the interrupt register update is correct as the NVIC is part of the Cortex M4 core, whereas the port registers are out on the peripheral bus.