That means the information supplied by ChatGPT is post #12 is inaccurate/fake. The GPIO2/GPIO23 of the sketch of post #1 belongs to Core 1 (by default).
Do you have any idea or sketch by which the said digital pins can be connected/directed to Core 0 and let the LEDs be blinking?
I'm lost - what don't you understand in this statement:
the GPIO (General Purpose Input/Output) pins on the ESP32 microcontroller are not tied to specific cores. Both Core 0 and Core 1 have access to and can control all the GPIO pins available on the ESP32
You have been told already in #2.
It is a typing mistake and should be ESP32S which is my board. I will re-check the pin-to-pin correspondences and will correct/adjust if any.
Never mind, he is known for insisting in only his own belief.
Do you have any idea or sketch by which the said digital pins can be connected/directed to Core 0 and let the LEDs be blinking?
See post #8 from @gfvalvo
Is your question how to create a task and assign it to a specific core ? (see xTaskCreatePinnedToCore())
See your own sketch in #1. If a sketch can toggle pins which you assume to be bound to a specific core, then one LED should not toggle.
Ok! I will exercise it and report the result.
here is a test code
TaskHandle_t task0Handle;
void setup() {
pinMode(2, OUTPUT);
pinMode(23, OUTPUT);
Serial.begin(115200);
//create a task on core 0 that will be execute task1Func() with priority 10
xTaskCreatePinnedToCore(
task0, /* Task function. */
"Task1", /* name of task. */
10000, /* Stack size of task */
nullptr, /* parameter of the task */
5, /* priority of the task */
&task0Handle, /* Task handle to keep track of created task */
0); /* pin task to core 0 */
}
void task0( void * pvParameters ) {
for (;;) {
digitalWrite(2, HIGH);
delay(1000);
digitalWrite(2, LOW);
delay(300);
}
}
void loop() {
digitalWrite(23, LOW);
delay(250);
digitalWrite(23, HIGH);
delay(250);
}
If the IO pins/lines of the ESP32S are not permanently tied to (default to Core 1?) any core, then there should be a software controlled switch/controller (Fig-1: installed by Espressif) that directs the IO line(s) either to Core 0 or Core 1 as requested -- is it correct?
Figure-1:
No - in the same way both cores have access to the memory, both cores have access to the peripherals or dedicated hardware
if there are potential access conflicts to handle, your code needs to deal with that and use usual techniques like semaphores
see FreeRTOS - ESP32 - — ESP-IDF Programming Guide v4.2 documentation and specifically the Semaphore API
D23 is an IO line on the header of ESP32S Module. There are two independent LX6 processors mounted (under the RF Shield) on the ESP32S Breakout Board/Module with their own GPIO23 IO line. The D23 line of the Module can be routed to the GPIO23 line either of Core 0 or Core 1. How is it possible to have this kind of changeover without a hardware switch conceptually similar to Fig-1 of post #32?
If you are talking about accessing the external common Flash Memory, then there must be (in association with controlling software) an external SPI Controller to route the SPI lines either of Core 0 or Core 1 to the IO lines of the Flash Memory (Fig-1).
Figure-1:
that's where you got confused. The Tensilica Xtensa 32-bit LX6 microprocessor has two cores embedded in one chip. it's not two separate microprocessors
that's what the die looks like (source Die Shots of Espressif #ESP32 « Adafruit Industries – Makers, hackers, artists, designers and engineers!)
Then the cores have intercommunication mechanism and all the necessary hardware to route the IO lines of the header pins of the ESP32S Module or of the external flash memory either to Core 0 or Core 1.
Referring to the block diagram of your post #3, it can be said that the ESP32S Board is composed of two CPU/MPU units/cores (having their ALU Unit, Register Set, and Sequence generator) and single unit of other hardware resources.
There are no two sets of IO lines as I thought before and all the confusions raised from there, which you have correctly pin-pointed and have successfully got me out of the trap.
see https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
key info
The ESP32 is a dual-core system with two Harvard Architecture core. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
The two cores are known as the PRO(tocol) Core and the APP(lication) core (pr "PRO_CPU” and “APP_CPU” and the two cores are interchangeable.
The address mapping of two cores is symmetric, meaning that they use the same addresses to access the same memory (one exception is the PID Controller). Multiple peripherals in the system can access embedded memory via DMA.
Each core can directly access embedded memory through both the data bus and the instruction bus, external memory which is mapped into the address space via transparent caching & MMU, and peripherals.
The address mapping, GPIOs are one of the 41 peripherals.
The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for routing signals from the peripherals to GPIO pads. 1. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads
I have tested your sketch and it is working in the sense that the LEDs are blinking as intended.
Few more questions/queries will be inline once I finish reading/understanding the newly arrived code lines/syntaxes of your sketch like xCreatePinnedToCore.
However, I am convinced that LED2 is being driven by Core 0 as it it outside of the loop() function and I need to verify it probably by reading the ChipIDs.
you can just add this line of code both in the loop and in the task0() function and you'll see which core is being used
Serial.printf("Task running on core %d\n", xPortGetCoreID());