Hello, I was curious about I2C bus low level signals, so I checked a communication sequence of reading status register (address 0x0F) and time registers of a DS3231 (DS3231RTC library) RTC. But there are a few things which I don't understand.
1.
uint8_t statusReg = 255;
RTC.readRTC(0x0F, &statusReg, 1);
Result:
Start bit, address, R/W, ACK. But what is the pulse marked with question marks?
2.
RTC.read(DateTime);
This starts a 7 byte read through the library, starting with 0x00 address (RTC_SECONDS).
Result:
First address was sent like in the first point. My question is that the second START is initated by the RTC module itself, right? So roles change, and after the second start, the ACK is coming from the uC?
3.
This is about twi.c. I found where the R/W bit is controlled for example for read:
// build sla+w, slave device address + w bit
twi_slarw = TW_READ;
twi_slarw |= address << 1;
And I understand that the blocking read/send is controlled through twi_state. For read:
// wait until twi is ready, become master receiver
uint32_t startMicros = micros();
while(TWI_READY != twi_state){
if((twi_timeout_us > 0ul) && ((micros() - startMicros) > twi_timeout_us)) {
twi_handleTimeout(twi_do_reset_on_timeout);
return 0;
}
}
And this leads to the interrupt vector for TWI where twi_status is altered and could became TWI_READY to exit the upper while cycle.
ISR(TWI_vect)
{
switch(TW_STATUS){
.
.
.
But what is this TW_STATUS and the switch cases values? TW_STATUS is already the TWI status register? I couldn't find a define or any clue for it.
Thanks in advance.
