Has anybody have any success with synthesizing Verilog from icestudio on the Vidor?
Not sure what you're trying to achieve however our source code is using systemverilog extensions which require an advanced synthesis tool. I would suggest you try quartus, the Intel tool we're using as well.
I think ICEStudio works only with Lattice FPGAs.
actually, IceStudio is a schematic / Verilog editor. The schematic gets churned into Verilog and then it kicks off whatever tools you have in your flow.
if you're planning to use that to generate code to be compiled on quartus then i don't see why that should not work.
as mentioned above, if on the other hand you want to compile our IP blocks on a different synthesis tool then likely it will fail because it may not have all the systemverilog extensions required and in the end the bitstream you will produce will not be compatible with Vidor anyway.
in any case if you want to try adding quartus support to icestudio i'm more than open to support you.
We're building a visual tool right now which will allow to program the VIDOR just by dragging and dropping blocks.
More news soon
Massimo/Dario - Do you have a rough estimate of when your team will be releasing the FPGA development workflows and/or software for the VIDOR board? There are a few projects I would love to start building for the VIDOR platform, but without an "Arduino approved" workflow, I'm hesitant to get started.
I'm not trying to rush you folks, I just don't want to start down a path that deviates so far from whatever standard workflow/s you have in mind that the average Joe/Joline struggles with it. The worst case scenario I can think of is to come up with a useful or fun project, have people try to duplicate it, fail miserably, and then decide that hobby electronics/programming is horrible. My itch to play with a new board shouldn't negatively impact others, heheh.
I know you folks are trying to work out how IP block source code and blaster emulation will look like with Intel. I'm also sure that there are a bunch of fun little quirks to developing your own dev environment + BSP for such a unique (or at least unique to the consumer world) device. Just hoping for updates or maybe even alpha releases for this nifty little board.
Command line Fpga compilation flow, along with source code for soft processor should be released next week. We're working on a major release that improves on JTAG communication speed and adds new features such as multiple fonts and graphic library support for neopixels. This is now under test and once is bulletproof, hopefully by end of the week, you're going to see some updates.
For web UI you will have to wait a bit longer. We announced it for October... Trying to be on track with that..
Thanks for your patience.
Hi Dario - curious about the state of the referenced FPGA RTL compilation flow?
it's really close to be released. we are polishing the last few bits. my target was this week but it's now over so stay tuned it's going to happen in days.
thank you for your patience!