This topic follows on from an adc input impedance question, but I think that it warrants a follow up. The consensus seemed to be that the input impedance is 100 Meg. taken from the data sheet.
I think that’s wrong.
Please see Figure 28.8 (attached). This shows a circuitry resistance of 1 - 100K. It is not 100 Meg. Quite a range but I think that this might be correct. There are two things:-
Why suggest a signal source impedance < 10K? With a 100Meg ADC input impedance, you could use virtually any circuit. You could probably even use cheese as wire. I think that only applies to the inner converter circuitry. It excludes all the intermediate wiring and the MUX.
Put an inverting op amp in front of the ADC input and couple with DC. Assume the standard R1 and R2 resistors to set the op amp’s gain, as G = R2/R1. I have found that I need much higher values of R2 to get a target gain than the simple formula suggests. I think that what’s happening is that R2 forms a potential divider with the lowish ADC input impedance, reducing it significantly, hence dropping the actual gain achieved. In the circuit I tried, I have to set a R2/R1 of 15 to get a 1V signal to scale to 5V. That’s 3 times the gain I anticipated. This suggests a significantly low input impedance. WAY less than 100Meg. Could it actually be 3750 Ohm (from a simple potential divider calculation)?
I will try to confirm this tomorrow by adding a buffer after the op amp. If I’m right, the actual gain should jump back up to 15 and swamp the input range.
Has anyone else found this behaviour for a directly coupled op amp?