Hi zebrawolf,
A workaround is to use dual slope PWM on both channels 2 (PA10) and 3 (PA11), but reverse the polarity on channel 2 and set their duty-cycles appropriately:
// Output 300kHz dual slope PWM on TCC0 with complementary outputs and dead time insertion
void setup()
{
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | // Enable GCLK0
GCLK_CLKCTRL_GEN_GCLK0 | // Select GCLK0 at 48MHz
GCLK_CLKCTRL_ID_TCC0_TCC1; // Route GCLK0 to TCC0 and TCC1
PORT->Group[PORTA].PINCFG[10].bit.PMUXEN = 1; // Enable the port multiplexer for port pins PA10 and PA11
PORT->Group[PORTA].PINCFG[11].bit.PMUXEN = 1;
// Select the port pin multiplexer switch to option F for TCC0/WO[2] and TCC0/WO[3] on port pins PA10 and PA11 respectively
PORT->Group[PORTA].PMUX[10 >> 1].reg = PORT_PMUX_PMUXO_F | PORT_PMUX_PMUXE_F;
TCC0->WAVE.reg = TCC_WAVE_POL2 | // Reverse the signal polarity on channel 2
TCC_WAVE_WAVEGEN_DSBOTTOM; // Dual slope PWM on TCC0
while (TCC0->SYNCBUSY.bit.WAVE); // Wait for synchronization
TCC0->PER.reg = 79; // Set the frequency of the PWM on TCC0 to 300kHz
while(TCC0->SYNCBUSY.bit.PER); // Wait for synchronization
TCC0->CC[2].reg = 40; // Output a 50% duty-cycle
while(TCC0->SYNCBUSY.bit.CC2); // Wait for synchronization
TCC0->CC[3].reg = 35; // Output a 43% duty-cycle
while(TCC0->SYNCBUSY.bit.CC3); // Wait for synchronization
TCC0->CTRLA.bit.ENABLE = 1; // Enable TCC0
while (TCC0->SYNCBUSY.bit.ENABLE); // Wait for synchronization
}
void loop(){}