Is there any feasible way to have two SPI lanes on Arduino?
Two SPI masters is possible, but it won’t make it any faster for two reasons:
- Only one hardware SPI master is available, creating more only by bit-banging (software-emulation) you can.
- All I/O is CPU-dependent, thus even two SPI masters would have been accessed sequentially anyways.
Or is there a different way to increase SPI throughput?
Since it’s a standard (sort of), adding lanes isn’t that simple; this is not PCI Express though.
And since this is a serial communication and no extra lanes can be added, your only option is increasing the bit rate which means increasing clock’s frequency.
The SPI master controller on an AVR micro can work at most at half the system’s frequency; so, as GolamMostafa said, 8 MHz (8 Mbit/s or 1 MB/s) maximum for most of the ATmega328P-based boards. Keep in mind this only accounts of an individual 8-bit “burst”; effective data rate is further decreased by any existing overhead (code execution in between transfers, busy slave, communication protocol such as commands and responses that aren’t part of the payload).
(I already did some changes to SPI library eg. replacing all “digitalWrite” with a much faster macro and changing SPI speed)
Only the second thing will help significantly because (again) the toggling on SCK and MOSI is done by hardware. Speeding up digitalWrite() I think just affects CS pin assertion/de-assertion.
Can you read data from the ADC at a clock rate (SCK) higher than 10 kHz (aka 10 kbits/sec)? The available division factors in the SPI.h Library are: 2, 4, 8, 16, 32, 64 or 128.
It should. I’ve also found in the datasheet that the maximum frequency is 3.6 MHz at 5V; so a prescaler of 8 (2 MHz) is needed.
10 KHz is the minimum because of the type of ADC (successive approximation) and because looks like it doesn’t have it’s own oscillator, instead the SCK line feeds up the required clock signal.