I was wondering if somebody could have a very quick look on my standalone scheme. This is my first, more complex, scheme that I've made and I have put some work into it.
Normally I wouldn't ask but it would be sin if my pcb doesn't work because of a small or dumb mistake in the scheme.
It is basically a standard Atmega328P-au by which I have added a few sensors such as the ADXL345 accelerometer, ITG-3200 and a micro sd slot with a low level shifter 74HC4050D.
Grumpy_Mike:
It's a bit small but looks fine.
The two caps on the crystal should be 22pF rather than 10pF but that is not vital.
Thanks!
Well the capacitors are actually 18pF because the crystal I ordered has this as load capicity. Is it still from importance to change to 22pF? It seems illogic to me.
Looks reasonable at first glance. What's your "sketch uploader"? I assume you've knocked up an adapter for an FTDI cable or some such.
The uSD may clash with ISP programming but that's easy to remove.
Any reason for using two 1k resistors for the LED2? I sometime do that to reduce the number of different components but I can;t see that being an issue here.
LED3 only has a 150R resistor, that's different to the 500R LED2 has. Different Vf on the LEDs?
I would add at least a ground connection on your ISP & Sketch interfaces, assuming the rest is always powered from the supply logic.
If you are going to bootload with an AVR ISP Mkii, you will also need the uC's VCC connected so the ISP knows what voltage level is being used.
(learned that from recent experience!)
Thanks for the feedback, I already tried to implement it.
I was planning to bootload as explained here: http://arduino.cc/en/Tutorial/ArduinoToBreadboard
but wasn't sure about the ground and power supply, thus now implemented both at the ISP and, as I call it "sketch uploader" basically where I upload my arduino code.
Graynomad:
That's clearer, I can read the values now.
Looks reasonable at first glance. What's your "sketch uploader"? I assume you've knocked up an adapter for an FTDI cable or some such.
The uSD may clash with ISP programming but that's easy to remove.
Any reason for using two 1k resistors for the LED2? I sometime do that to reduce the number of different components but I can;t see that being an issue here.
LED3 only has a 150R resistor, that's different to the 500R LED2 has. Different Vf on the LEDs?
Rob
I don't know where the 1K resistance came from, though thanks for noticing. And what do you mean by the possibility of clashing between the ISP and the uSD, would this cause a problem when programming the bootloader without having the uSD physically inserted into the slot? Though the level shifter is still active, but would it matter? If so, how to solve this problem,a switch in between doesn't seem very efficient and a transistor can't solve this without making a few modifications i guess?
Keep in mind, when calculating crystal capacitors, load capacitance isn't the target capacitor size, it's part of the equation:
C1 = C2 = 2 * (CL - CP)
Where C1 and C2 are your two capacitors, CL is the load capacitance in the crystal datasheet, and CP is the parasitic capacitance of the circuit.
CP is such a small value, and very difficult to know in advance, that I usually figure it being somewhere between 5 and 8pF. From what I've been able to see, this is pretty typical. As long as it isn't wildly off, you'll be well within tolerance specs of the capacitors anyway.
SirNickity:
Keep in mind, when calculating crystal capacitors, load capacitance isn't the target capacitor size, it's part of the equation:
C1 = C2 = 2 * (CL - CP)
Where C1 and C2 are your two capacitors, CL is the load capacitance in the crystal datasheet, and CP is the parasitic capacitance of the circuit.
CP is such a small value, and very difficult to know in advance, that I usually figure it being somewhere between 5 and 8pF. From what I've been able to see, this is pretty typical. As long as it isn't wildly off, you'll be well within tolerance specs of the capacitors anyway.
Hmm, quite hard to figure out the exact CP value then, though from your feedback I could interpret that my current values are within reasonable boundaries.
what do you mean by the possibility of clashing between the ISP and the uSD
The uSD output goes to MISO which also goes to the ISP connector. If a card was in place it might be driving that signal at the same time as the programmer is.
Also with all the other signals bouncing around who knows what that will do to the SD card?
But as I said it's easy to remove the card so that's all you have to do, and if this is only for the bootloader you won't have card in at that point anyway I would think.
BTW I just noticed LED1 has a 1k resistor as well and that's driven by 3v3.
MISO being connected without buffering should be okay. CS to the card will be inactive while any other device is driving MISO, so no interference.
I'd be more worried about SCK going thru LED1 and introducing noise onto the CS line.
I appreciate CS going low to enable LED1 and show SCK activity - I would connect 3A to 5A, and use 5Y as that ground instead.
CS to the card will be inactive while any other device is driving MISO
Maybe, maybe not. It's driven by SS which will be floating, what does the 4050 do with a floating input? The data sheet shows no pullup/dn resistors so I think it's likely to go either way.
Yes LED1 is potentially a problem, fixed as you say.
Thus, only changing the ss pin by adding a pull up to the 5V. Should I still change pin 5Y and connect 3A with 5A, I don't really see the purpose of it anymore.
I did update the schematic again and designed the board with it. Hopefully I didn't forget anything stupid, though I'm still a bit confused about the connections and ground of the level shifter, in particular the ground of 5Y and if I need to connect pin 3A with 5A.
C7 and C8 are decoupling caps for the processor. They should be as close as possible to the VCC/AVCC and AREFpins. If you follow the path from C7 to AREF it goes half way around the board.
C5 has too long a path to the crystal, swap C5 and C6 so the tracks can be nice and short.
Also all power tracks should be wider.
I gather it's been auto-routed, they always do a crap job so I'd tidy up a lot of tracks.
C7 and C8 are decoupling caps for the processor. They should be as close as possible to the VCC/AVCC and AREFpins. If you follow the path from C7 to AREF it goes half way around the board.
C5 has too long a path to the crystal, swap C5 and C6 so the tracks can be nice and short.
Also all power tracks should be wider.
I gather it's been auto-routed, they always do a crap job so I'd tidy up a lot of tracks.
Rob
Thanks Rob, you're really helping me out here! I still got a lot to learn when it comes to board design, but topics like these are very nice!
I took your advice and routed a big part myself now, with wider tracks on it though, I still used the auto route because of my lack of awareness.
