@johnny_wee,
You must be joking. Do you really expect such a ratsnest of Dupont wires to work ?
I have built with proper ST Core. And am able to use up to date Adafruit GFX files e.g. v1.9.0
If I build with the weird RogerClark Core I have to downgrade to Adafruit_GFX v1.7.5
The compatability is nothing to do with MCUFRIEND_kbv. It is because Adafruit has added dependencies that are not relevant to most third party libraries like MCUFRIEND_kbv.
Anyway, since I don't know where you got your PIONSCORE special:
// #################################### STM32 PIONSCOR #######################################
#elif defined(USE_PIONSCOR_BLUEPILL) && (defined(__STM32F1__) || defined(ARDUINO_BLUEPILL_F103CB)) // MAPLECORE or STM32CORE
//LCD Pins : | D15| D14| D13| D12| D11| D10| D9| D8| D7| D6| D5| D4| D3| D2| D1| D0|
//BLUE PILL: |PB15|PB14|PB13|PB12|PB11|PB10|PB9|PB8|PB7|PB6|PB5|PB4|PB3|PA15|PB1|PB0|
//LCD Pins : |RD |WR |RS |CS |RST |
//BLUE PILL: |PA0 |PA1 |PA2 |PA3 |PA8 |
#warning SSD1963 on USE_PIONSCOR_BLUEPILL
#define USES_16BIT_BUS
#if defined(__STM32F1__) //weird Maple Core
#define REGS(x) regs->x
#else //regular ST Core
#define REGS(x) x
#define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
#endif
#define WRITE_DELAY { }
#define READ_DELAY { RD_ACTIVE; }
//
#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
#define PIN_OUTPUT(port, pin) {\
if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \
else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
}
#define PIN_INPUT(port, pin) { \
if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
}
#define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
#define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
#define RD_PORT GPIOA
#define RD_PIN 0
#define WR_PORT GPIOA
#define WR_PIN 1
#define CD_PORT GPIOA
#define CD_PIN 2
#define CS_PORT GPIOA
#define CS_PIN 3
#define RESET_PORT GPIOA
#define RESET_PIN 8
// configure macros for the data pins DB2 on PA15. All others on PB0-1, PB3-15
#define BMASK 0xFFFB
#define write_16(d) { \
GPIOA->REGS(BSRR) = (1<<15) << 16; \
GPIOB->REGS(BSRR) = (BMASK) << 16; \
GPIOA->REGS(BSRR) = ((d) & (1<<2)) << 13; \
GPIOB->REGS(BSRR) = (d) & BMASK; \
}
#define read_16() ( ((GPIOA->REGS(IDR) & (1<<15)) >> 13) | (GPIOB->REGS(IDR) & BMASK) )
// PA15 PB15-PB8 PB7-PB3,PB1-PB0
#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xF0000000); GP_OUT(GPIOB, CRH, 0xFFFFFFFF); GP_OUT(GPIOB, CRL, 0xFFFFF0FF); }
#define setReadDir() {GP_INP(GPIOA, CRH, 0xF0000000); GP_INP(GPIOB, CRH, 0xFFFFFFFF); GP_INP(GPIOB, CRL, 0xFFFFF0FF); }
#define write8(x) { write16((x) & 0xFF); }
#define write16(x) { write_16(x); WRITE_DELAY; WR_STROBE; WR_IDLE; WR_IDLE; }
#define READ_16(dst) { RD_STROBE; READ_DELAY; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
The RogerClark Core is a nightmare. Why don't you use the official Core from STMicroelectronics ?
ST are the actual manufacturers of the STM32 chips. ST support the official ST Core
David.
