I can barely get the grasp of SPI protocol, I know that in order to read we must send clock pulses right ?, so the clock pulses we must send 16 clock pulses repeatedly 8 times for 8 chips as the clock pulses become shifted, so on the PCA9702 8 bit register it will take the first 8 pulses ad ignore the other 16 right ?, how lost am I ? please correct me !
I meant the PCA9702 will take 8 clock pulses to read and ignore the other 8 pulses, however the ensuing chips 9701 will take the 16 clock pulses and read the whole port
I get it, we are sending byte (8 bits) but it takes 15 times sending 8 bits to cover all chips, so every iteration means is reaching that specific chip, for example i=0 read first chip, then i=1 and 2 reads second chip as this takes 16 bits, iteration 3 and 4 reads chip 3 and so on until all 8 chips are read
seems to be reading all inputs, I had to raise the pullup voltage up to 24 vdc, when I apply GND I immediately observe the status
thank you very much for the help, you guys are great !
this board already has input resistor network, it is supposed to be fed by 24 vdc, I was using 12 vdc
this board already has input resistor network, it is supposed to be fed by 24 vdc, I was using 12 vdc
Well not sure what is going on with the inputs since you have only shown partial schematics but since you are using 3.3V for Vdd the input high/low thresholds will only be 1V apart.
I get it, we are sending byte (8 bits) but it takes 15 times sending 8 bits to cover all chips
Exactly!
Regarding the CS being all connected togheter
It would not make sense to have individual CS's The way you are doing it is correct.
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