Hi Eric
1)In the PATT register, setting the pattern generator's bit PGE4 (Pattern Generator Enable Channel 4) simply overrides the channels output, setting the output high or low depending on the value defined by the bit PGV4 (Pattern Generator Output Value Channel 4).
The TCC0 alternates cycles on channel 0, both aligned to the rising edges of the input signal. On one cycle TCC0 generates standard a 1250us pulse, on the other it generates a 2500us pulse, but the TCC1 timer actives the TCC0's pattern generator to set the first 1250us of the pulse low. This gives the output of a 1250us pulse with a phase delay.
- I'm not seeing this behaviour on my board. If I disconnect the PA19 input both PA22 and PA23 outputs go low.
There is an issue that if the input pulses are stopped, the TCC1's ISR and the TCC0's circular buffer can get out of sync with one another.
- Unfortunately, in this instance the DAMC won't work, as it doesn't have the same flexibility as an interrupt service routine.
The problem is that the PGE4 bit in the PATT register needs to be set every other cycle by the TCC1 overflow (OVF) and cleared by the match compare 0 (MC0). This requires two DMAC channels, one to trigger on TCC1 overflow and the other on match compare 0, however the two channels cannot simultaneously share the single destination PATT register.
The TCCx timers can generate events on the event system, to trigger the ADC. The DMAC can used to automatically copy the results from the ADC into memory.