Whether it's normal is not really the question. The first question is how much noise your application will tolerate. If the present performance is sufficient, forget it and move on. If it's not, then you need to identify the sources of the noise and deal with them.
Did you analyze the sources of the noise you're seeing? How did you conclude that a CLC filter on the input was the way forward? If that is indeed the correct approach, did you model the performance of the filter over a relevant frequency range (e.g. spice sim)? If so, have you verified that the simulation parameters are representative of the real-world components and circuit layout including parasitic capacitances, inductances and resistances?
I don't know what the regulations are that apply to this product and the regions it is supposed to be sold in. I also don't see any measurements of the EMI behavior of this circuit; you've only shown us plots of power supply line noise. That doesn't say much about EMI/EMC performance at all. Note that this also involves testing in the actual housing/physical setup of the end product. I see you're presently working with a prototype PCB that's only populated in part. I don't see how you could do a final EMI assessment of this setup.
Please refer to page 13 of the datasheet and the instructions provided for the selection of the output cap etc.
Capacitors are not created equal. ESR can differ from type to type. Parasitic inductance and parallel parasitic resistance also differ, and moreover can vary according to PCB layout.