Hello,
I would like to evaluate this core in the FPGA but don't know if some have tried before or if there is resource for this board specifically since most of resources for RiscV in fpga are for xilinx or lattice FPGAs but I guess they are compatible as they are written in hdl code (not sure about peripherals).
Also I'm not sure about how to debug and evaluate software with this core. I guess will be via jtag and some eclipse plugin but never tried and don't know how will be with the MKR vidor and intel fpgas.
Finally, what about the memory?. it will be inside fpga or I will need some external memory interface?.
There is some resources for Risc five cores in internet to evaluate them in FPGA like but not sure about what will be the best:
GitHub - YosysHQ/picorv32: PicoRV32 - A Size-Optimized RISC-V CPU (they are evaluated for xilinx boards)
GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (I have seen this core in lattice FPGAs)
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (is multi platform and was implemented in DE-0 intel fpga board but not sure about the debug interface)
Regards,
Juli.