I was looking for thoughts on whether we can use C++ structures as a means of sending data between the two cores. I'm generally thinking of using the M7 to manage communications and setup the structure, then when triggered it's just use a single byte across the RPC to start the M4 running. When the M4 is complete it can send a single byte back and the structure will hold all the actual data.
Thoughts? It seems like this would require the two sketches to align on how they're setting up the data and since that's a compile-time decision I'm not sure it would work. Likewise, I'm concerned the SRAM partitioning might make the handle for it such that it can't be simply shared between the two. Is this a solved issue and I'm just missing something?
Have you check the RPC library?
Yes, I've read that document multiple times. It doesn't mention anything about sharing structures between the cores.
It uses some version of msgpack under the bonnet to serialise what you pass via RPC.send() or call() so it should work if you follow the msgpack api protocols for custom pack/unpack. That being said, I think the RPC library in general is a little flaky (eg it doesn’t return error codes from the underlying tech it uses in all cases) so YMMV.
Yes! I want to do almost exactly the same thing with a very similar strategy. My one difference is that I'd like the M4 to return a 2 dimensional array of doubles of a predetermined and fixed size known at compile time.
Nick, what approach did you take? Did you ever find any useful docs to illuminate things? Can the basic RPC parameter passing handle 2D arrays of doubles?
I have the additional related question of understanding how to minimize any overhead and interruptions of the M4 while this timing sensitive data collection request is being serviced.
TIA, Joe