Structured Text Challenge; PLC IDE - 180 degree phase lag between PWM channels

Official Hardware Opta
1

EDIT:
feeding PWM OUT to f_trig will generate 1s on falling edge, but getting that to pass correctly through shared outputs, global vars, etc isn't immediately obvious. Will update.

UPDATE: Better make sure that code is reaaallll clean

This one is for the gurus: I'm using the PLC IDE, therefore structured text language, to drive the A0602 PWM channels in the kHz range. I need two of my channels to be inverted relative to the other two. From what I can tell, this is going to require a timer that starts synchronously with my first signal (say, PWM1 and 2) and triggers the other two channels after half the period has passed.

I have two issues:

  1. no TON type in the PLC IDE variable types library
  2. where is all of the documentation on code blocks like f_trig????

Thanks in advance!

2

Have you considered a inverting IC such as a 74HC04?

4

Oh ofc. I'm trying to be clever and get the OPTA to do it for me, though. Why buy a part when you can spend six hours forcing a machine to do something that, for some reason, the developers never thought would be useful?

Spite. Spite and a hunger for forbidden knowledge

5

bingo. You're welcome.

if toggle and not prev then
	GO:= NOT GO	;
	DIN1:=true;
end_if;
prev:=toggle;
p1:=p_1;
p2:=p_2;
p3:=p_3;
p4:=p_4;
if GO2 then
	GO2trig:=GO2trig+1;
	else
end_if;	
if GO then	
	d1:=d_1;
	d2:=d_2;
	else
	d1:=0;
	d2:=0;
	d3:=0;
	d4:=0;
	GO2trig:=0;
end_if;
if GO2trig=50 then
	d3:=d_3;
	d4:=d_4;
	DIN1:=false;
end_if;	
if d1>0 then
ALED1 :=true;
else ALED1:=false;
end_if;
if d2>0 then
ALED2 :=true;
else ALED2:=false;
end_if;
if d3>0 then
ALED3:=true;
else ALED3:=false;
end_if;
if d4>0 then
ALED4:=true;
else ALED4:=false;
end_if;