UNO R3 on 3.3 VCC

Official Hardware Classic UNO R3
1

Can I run MEGA328 on 3.3V?

The data sheet shows operating parameters at 3.3v but are there any downfalls? Many pins on the MEGA328 are going into a 3.3v FPGA. I don't want a boat load of level translators.

Software is being developed on a UNO R3 but the target hardware is a MEGA328 programmed with the HEX file from the UNO.

2

Operating frequency.

3

16mhz

4

See section 28.4 of the data sheet(very little info provided; somewhere, I've seen more, but it might have been an errata sheet). The lower your voltage, the lower frequency you can run the CPU. For 3.3, I think you'll need to get down around 10 MHz. If you're using UARTS, TWI, SPI, etc. you'll need to look at the effects of CPU clock change.

5

Typically when running at 3.3V a frequency of 8 MHz is used. For example the Pro Mini that is "retired" but variants are still available from places like Adafruit and clones on Amazon.

The main use was lower power, but it could be a solution to you problem if the lower performance is tolerable.

6

You can modify an Arduino UNO (or copy) to run at 3v3. I have one on the bench that I modified. The basics are here:

You would be outside the manufacturers specs to run 3v3 @ 16Mhz. Assuming the slope is linear in the speed grade graph in the datasheet, the max recommended clock for 3v3 is around 13.333Mhz.

That sits nicely above the magic 11.0592Mhz crystal frequency that divides down nicely for lots of UART baud rates.

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7

@andy_ee:

Have a look at this product from SeeedStudio, it works on both 5V and 3.3V (switchable).

Guglielmo

8

A 328P at 3.3V and running on 16 MHz is officially out of spec :wink:

9

I totally agree, but ... it's an official product supported by Seeedstudio and works very well.

Moreover, no one is stopping you from setting the clock divider to run the rest of the application at 8MHz as a very first step ... :wink:

void set_Clock(void) __attribute__((naked)) __attribute__((section(".init3"))) __attribute__((used));

void set_Clock(void) {
  cli();
  CLKPR = (1 << CLKPCE) | (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0); // Enable change
  CLKPR = (0 << CLKPCE) | (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (1 << CLKPS0); // Prescaler 2
  sei();  
}

Guglielmo

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10

Thanks to all for the suggestions.

After talking to Altera (now Intel), they said to just put 1k series resistors on all the 5v input lines to the FPGA.

Works for me as 3.3v causes me some other issues beyond the clock speed.

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