Power P-channel MOSFET circuits when operating from a positive supply usually have the supply voltage on the source and the load on the drain. This makes the drain more negative with respect to the source and supplies the correct bias for a P-channel device. However, the Reference Schematic shows the supply, USBVCC, on the drain.
There is also the problem of the diode formed by the source connection to the device substrate. This places a diode across the drain and source with the anode connected to the drain. This is clearly shown in the T1 device symbol in the schematic. Imagine what happens when the MOSFET channel stops conducting because
the op-amp comparator senses Vin. Because USBVCC is on the drain, it is still connected through the forward biased diode.
If USBVCC was on the source and the drain was connected to the +5V rail, then the gate voltage would be 5 volts more negative than the source when the comparator was low and the MOSFET would conduct. When the comparator was high then both gate and source would be near 5 V and the voltage from gate to source would be near 0 V and T1 would be off. Also, the source to drain diode would be reverse biased. I believe that this is how the circuit should work.