Using the ATSAMD51 to measure a fast 1usec pulse width

Projects Programming
17

Thanks MartinL
I had based my other code which is above in post 12 on your post

SAMD51 TC PWP mode for measuring frequency - Inputs? - Using Arduino / Microcontrollers - Arduino Forum

Which you did awhile back and it was very helpful !!
This code works very well and you have it in a 32-bit counter which is great!
Have you ever got the PW capture mode working? Best I can find is that nobody has been successful with that? Because in my situation I do not have a running frequency only a one time single pulse. This makes using the OVF flag on a long single pulse impossible.
Because the flag is coming from two places, CC0 and CC1 the OVF count gets messed up.
That is why I would like to use the PW capture mode since it only measures one thing, the pulsewidth and not the period. In this case the OVF would only come from one counter CC0 which I think I could then count the number of OVF and measure longer pulses. This was important in the 16-bit counter but the 32-bit counter could make the OVF unnecessary. At a 120MHz clock it gives me a 35.8sec pulse length where the 16-bit counter only gave me a 546usec pules before it OVF. If in my setup I get a 35sec pulse something else is very wrong :slightly_smiling_face: So 32-bits are great!!

I do have a question on the code. In the 16-bit counter example you posted in the past you had all of this:

// Set up the generic clock (GCLK7) used to clock timers 
  GCLK->GENCTRL[7].reg = GCLK_GENCTRL_DIV(1) |       // Divide the 120MHz clock source by divisor 1: 120MHz/1 = 120MHz
                         GCLK_GENCTRL_IDC |          // Set the duty cycle to 50/50 HIGH/LOW
                         GCLK_GENCTRL_GENEN |        // Enable GCLK7
                         //GCLK_GENCTRL_SRC_DFLL;      // Generate from 48MHz DFLL clock source
                         GCLK_GENCTRL_SRC_DPLL0;     // Generate from 120MHz DPLL clock source
                         //GCLK_GENCTRL_SRC_DFLL1;     // Generate from 100MHz DPLL clock source
  while (GCLK->SYNCBUSY.bit.GENCTRL7);               // Wait for synchronization

But in the 32-bit version which is almost identical you did not need the above??
So I guess when you use GCLK[0] none of that is required or is it happening somewhere else?
Just trying to understand.

Anyway thank you very much for your help with all of this!!!