Watchdog timer (interrupt mode) related question

[amazed]

Hello, I was looking at several watchdog timer interrupt related examples.
Usually they do the following to set interrupt mode and/or change prescaler (e.g. before going to sleep).
I added my comments regarding my concerns.

// clear various "reset" flags
//ADDED comment --> this is OK, this clears WDRF also, related info from datasheet:
//"WDE is overridden by WDRF in MCUSR. This means that WDE is always set when
//WDRF is set. To clear WDE, WDRF must be cleared first."
MCUSR = 0;     

// allow changes, disable reset
//ADDED comment --> this is not exactly clear why WDE needed to set here, if I get it
//right it has nothing to do with disabling wdt reset
//ADDED comment --> set only WDCE to start the timed sequence would be enough right?
WDTCSR = bit (WDCE) | bit (WDE);

// set interrupt mode and an interval 
//ADDED comment --> this is OK, before four cycles are done, (only) interrupt mode
//and the desired prescaler is set
WDTCSR = bit (WDIE) | bit (WDP3) | bit (WDP0);    // set WDIE, and 8 seconds delay
wdt_reset();  // pat the dog

So the "| bit (WDE)" during first WDTCSR set is some leftover from another example where system reset was also used?

Thanks in advance.

[J-M-L]

you configure your watchdog timer through the WDTCSR register but in order to enable a safety setup mode for this register's configuration (that will last 4 clock cycles) you set WDCE and WDE high before attempting any changes to the watchdog register.

so the real changes are

WDTCSR = bit (WDIE) | bit (WDP3) | bit (WDP0);    // set WDIE, and 8 seconds delay

EDIT: I found where I made a note from this

read Tutorial: Basic Watchdog Timer Setup and the attached PDF

[amazed]

Thanks for the tutorial link, good one!

Since then I figured, that datasheet example tries to imply for this method, because for turning off WD completely, example sets WDCE and WDE first.

void WDT_off(void)
{
  __disable_interrupt();
  __watchdog_reset();
  /* Clear WDRF in MCUSR */
  MCUSR &= ~(1<<WDRF);
  /* Write logical one to WDCE and WDE */
  /* Keep old prescaler setting to prevent unintentional time-out
  */
  WDTCSR |= (1<<WDCE) | (1<<WDE);
  /* Turn off WDT */
  WDTCSR = 0x00;
  __enable_interrupt();
}

Although this could not be interpreted directly just by reading the WDCE and WDE bit desciptions in the datasheet (at least for me).

Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.

Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure