I've been looking for a microcontroller that can execute code loaded into its SRAM. However, I do not know what to look for!
Many people would say it all boils down to architecture - Harvard doesn't work like that (because it has two physically separate memory banks for code and variables) While Von-Neumann does (shared SRAM)
However, there are exceptions -- the DUE, which uses the Harvard Architecture, is perfectly capable of running code from its SRAM.
The chip I'm looking at currently is the ESP-32, which uses a Harvard architecture.
So, how can I tell (without buying one and testing it, obviously )?
There's the datasheet...
A pure "Harvard" architecture means that the processor has separate buses for the instruction and data path, and probably can't run code from RAM (unless it has some RAM memory on the instruction bus...)
A pure "von Neumann" architecture has a single bus for data and instructions and can usually run from RAM.
A "modified Harvard" architecture has multiple memory buses, but they share an address space. By being able to simultaneously fetch instructions on one bus and data on the other bus, you get certain performance improvements, but you can usually still execute instructions from the data memory. (most of the ARM Cortex M cpus fall here.)
I don't know about the ESP32, and relying on a badly written datasheet that was probably translated from another language is ... worrisome; The datasheet says:
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