Yeah, in your d/s, TWI/I2C is now in Table 29.7, and it still says 0.7*Vcc. However, if 3.3V works,
then I'll use it :-).
It seems to me the d/s is a little equivocal about the SCL pin being open-drain. Sec 22.2.2
doesn't specifically say SCL is open-drain for the 328P, but implies it. Sec 24.4 reinforces this idea.
Sec 22.5.1 implies the internal pullups are disabled.
pg. 210:
22.2.2 Electrical Interconnection
As depicted in Figure 22-1, both bus lines are connected to the positive supply voltage through pull-up
resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements
a wired-AND function which is essential to the operation of the interface.pg. 213:
22.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order
to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission
at the same time.
......
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all
masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the
Master with the shortest high period. The low period of the combined clock is equal to the low period
of the Master with the longest low period. Note that all masters listen to the SCL line, effectively
starting to count their SCL high and low time-out periods when the combined SCL line goes high
or low, respectively.pg. 215:
22.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads
can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the
I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones.pg. 236:
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one,
the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate
limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions
are terminated, regardless of any ongoing operation.