Basically, I plan on using an ESP32 to drive 4x boards, each consisting of 8x TPIC6B595s (w/ 74HC125 as a buffer per chip) that will be used to drive 15x 5V 28BYJ-48 stepper motors, giving a total of 32x TPIC6B595s, 4x 74HC125s and 60x 28BYj-48s. Does the below make sense for this purpose? The first SR_BOARD will receive the input from ESP32_BOARD_OUT, and every SR_BOARD after that will receive its input from the previous board etc.
Am I missing anything? I have the 0.1uF decoupling caps, however many other designs on these forums suggest the use of another capacitor, what is the purpose of this and where should it go?
Also, in regards to the 74HC125 buffer, I do not really understand its purpose, nor how it achieves this purpose...? (All I know is that it is a buffer chip and it's necessary? But this doesn't seem to match my idea of a 'buffer' in memory).
Fan-out is likely not an issue with Cmos, if wiring is kept short.
Level conversion is more important, because TPIC chips are 5volt only (>=4.25volt for a HIGH).
The ESP is 3.3volt logic.
If you would use a 5volt Arduino, then the 74HC125 would not be needed.
I have controlled a chain of 24 TPIC chips with a Nano @4Mhz SPI.
Leo..
Fan-out itself is less likely to be a problem, because your shift-registers are wired serially. out-in-out-in- etc...
The clock, latch etc are one long wire with a lot of branches on and between boards, that’s more likely to be an issue.
To address both issues, you need to look at buffering all the signals, and noise mitigation. The current layout may seriously affect your maximum clock & data rate.
It’s not impossible, but I wouldn't start this way.
Buffering may also be a convenient place where you introduce level conversion.
Good luck. If you stick with this concept, have a read up on high-speed serial busses.
It seems like fan-out may not be something I have to deal with, but logic level conversion is. But as CrossRoads and lastchancename have pointed out, maybe I can introduce the 74AHCT124 as a line driver to overcome this on the first board (although means my boards wouldn't be as modular, so may be worth replacing all of the 74HC125s with these....)
I'll look into high-speed serial busses in the next couple of days.
Lastchancename, sorry for my naivety, but what do you mean by all the signals? With a buffer on each chip, does this not cover the clock, data and latch signals - what else am I missing?
TomGeorge, I haven't yet. However I have daisy chained 12*74HC125s as a start. I won't be ordering any PCBs, just enough parts to continue mucking about on a breadboard at this stage. Just got bored whilst waiting on parts to arrive in Aus from China...
Exactly, you’re on the money. But CLK, DAT, and LATCH all take different paths.
The daisy-chain solves some issues like fan-out, but extends the signals differently for each wire... some are multi-drop, some are paralleled, and some are daisy-chained sequentially.
As the serial speed goes up, especially over longer or convoluted buss paths, you’ll have different waveform ‘shapes’, as they rattle through the interconnected boards (crosstalk, capacitance, voltage drop etc). This can skew the arrival of CLK & DAT relative to each other, and noisy edges may appear as stray CLK or DAT values.
This is where buffering and synchronous data helps, as long as the signals are clean - with nice sharp edges etc.
The buffering mentioned here isn’t a lengthy ‘buffer’, but simply the ability to reclock, or synchronise the three buss lines so they reliably arrive at the same moment.
