5V <-> 3.3V Level Shifter

Other Hardware General Electronics
1

I'm trying to implement a level shifter for an SPI bus using a Mega328P @ 5V that will interface with other SPI devices (also at 5V) as well as a MicroSD card @ 3.3V.

The basic level shifters won't work as they all assume that there will only be one slave device on the SPI bus and don't tristate the MISO signal.

I've put together a quick schematic of a 74HC125 circuit as shown:

LevelShifter.png

Am I on the right track with this design or is there something that i've not thought about such as switch on times of the buffers.

Thanks for looking.

LevelShifter.png

2

I would not enable the MOSI and SCK translators with the SS line. I think those enables should be grounded so they are always on.

As part of the initialization process, as I recall it, the master sends a series of clocks while SS is not asserted. The way you have it now, those would not go through. Also, I don't know how the SD card will react if those lines go floating.

It's only the MISO line that needs to play well with others.

3

I second that recommendation. MOSI and SCK always alive going to the slave, only MISO needs to be gated back on to the bus. If you do buffer MOSI and SCK, add pulldown resistors so the lines are not floating and spuriously changing.

4

Your "5V_MISO" has a 3.3V logic level. Will that work with a 5V input?

5

Thanks for the replies. I was undecided about permanently enabling the buffers for MOSI & SCK.

@aarg: I hear what you're saying about MISO. I'd prefer it if MISO was closer to 5V.

I've just had a look at a 74HC367 which looks similar to the 74HC125 but has tri-state outputs. It would mean adding pull ups to both sides, but potentially fixing the MISO voltage level.

It also has 2 separate sets of buffers allowing MOSI, SCK & SS to be permanently enabled whilst using SS to control MISO.

LevelShifter2.png

LevelShifter2.png

6

I don't think that makes the circuit better. Pullup resistors may not allow for the kind of speed that a regular totem pole output provides, which is low impedance in both directions.

The 3.3V MISO has worked fine in millions of SD card modules with level shifting built in. I've never heard of that being a problem.

I think your first circuit should be fine if you have the SCK and MOSI shifters permanently enabled.

7

Thanks for the feedback. I guess the 3.3V MISO signal level is just something to be aware of, and I'll configure the chip to permanently enable SCK and MOSI.