Adding a new IP Block in Vidor FPGA

Official Hardware MKR Family MKR Vidor 4000
1

I would like to load and use an extra IP Block such as vilhelmgray/Monostable: Monostable is a Verilog implementation of a monostable multivibrator. - Monostable - Codeberg.org.

Could you please advise on steps needed to integrate and use this?

  1. Is there any way to compile this separately and load it, in addition to existing IP Blocks?

  2. If not, do I need to download and re-compile VidorPeripherals with my new IP block, or do I need to recompile VidorBitstream and other code also?

Thank you for your help!

2

You do have to recompile the whole FPGA project that you want as a basis for your additions.
There are no ways of adding IP separately, at least not with the Cyclone 10 LP.

3

Hi VStrakh, thank you for your clarification!

Does the official Github repository contain all the necessary files to make a complete recompile with my new additions / extensions?

4

Yes, the repository has everything, check the pinned topic: [WORKFLOW RELEASE] Vidor sample projects are opensource!

But note that the project is using some Intel IP that requires licensing (Nios II /f and 16550 UART), so there are two versions of the project - the full, and the "lite" one. The "lite" falls back to free Nios II /e, and disables the UARTs.
I'm not quite sure why the paid uart was used in the first place, you will have to either deal with it (have the license, or replace with other implementation), or tolerate the cores missing.