And page 18 of that document lists the protocol for communicating with it.
I'm confused just two bits into it though.
What's buffered vs unbuffered operation? In buffered mode is there some other pin I need to trigger to actually output the analog voltage for the byte I just sent it? What's the point of that?
And output gain... If I set that to 2x, how does that even work? How can the chip output 2x the reference voltage I put into it?
Sorry if these arre easy questions covered elsewhere in the datasheet. I just have five days to finish the design of this circuit and I've suddenly found myself needing to do a crash course on SPI communication and using DACs.
The input buffer amplifiers for the MCP492X devices
provide low offset voltage and low noise. A configuration
bit for each DAC allows the VREF input to bypass
the input buffer amplifiers, achieving a Buffered or
Unbuffered mode. The default value for this bit is
unbuffered. Buffered mode provides a very high input
impedance, with only minor limitations on the input
range and frequency response. Unbuffered mode
provides a wide input range (0V to VDD), with a typical
input impedance of 165 k[ch937] w/7 pF.
Not sure what an offset voltage is. And impedance is still a word that confuses me. But if the default mode is unbuffered maybe I don't need to worry about it. I'm not too concerned about noise considering the sound will be output through a piezo.
There's something else I was wondering about the dac that just occured to me...
If I write to this dac by writing 16 bits at a time, and I don't need to set a latch bit when I'm done, then does that mean the dac just waits for 16 bits and then outputs whatever it got?
If that is the case, what happens if a little noise gets into the clock line and the dac misses a bit? Wouldn't all the rest of the output be really screwed up because it would be a bit behind?
That's why I was looking at the communication protocol in the first place... I was trying to see if there was something in that which would prevent such a problem.
And scrolling a bit further down the document, I see a diagram of what one might see on an oscilliscope as one is sending data. And I see that that chip select line goes low just before the first bit is sent, and then it goes high again after...
That means CS may act like a latch. And that would prevent an issue like the one I was worried about.
And that also means I must connect the CS pin to the Arduino.
That was a question I had in another thread about SPI comunications. I thought I might be able to simply tie that pin on the dac low, since it was the only chip I was going to be talking to, and use the CS pin for something else. But I guess I can't do that.
[edit]
...then again, I see LDAC also triggers once 16 bits have been sent. And I think that is in fact, the latch. So maybe I can pull the CS pin low. But I would need to use the latch...
But that doesn't seem to be in fitting with SPI which specifies a CS line but makes no mention of a latch line...
The MCP492X utilizes a 3-wire syncronous serial
protocol to transfer the DACs' setup and output values
from the digital source. The serial protocol can be interfaced
to SPI? or Microwire peripherals common on
many microcontrollers, including Microchip's
PICmicro® MCUs & dsPICTM DSC family of microcontrollers.
In addition to the three serial connections (CS,
SCK and SDI), the LDAC signal syncronizes when the
serial settings are latched into the DAC's output from
the serial input latch. Figure 6-1 illustrates the required
connections. Note that LDAC is active-low. If desired,
this input can be tied low to reduce the required connections
from 4 to 3. Write commands will be latched
directly into the output latch when a valid 16 clock
transmission has been received and CS has been
raised.
I guess that answers that question then. I should stick a 10K pulldown resistor on the DAC's LDAC pin, and the CS pin must be connected to the Arduino along with the SDI and SCK pins.
I wonder why the wave shield has a connection to the LDAC pin as well though.
I also am still confused about those buffers and that 2x gain thing.
I think I get why the buffers and LDAC pin are there actually...
Well I don't get why one is there on this particular chip... but there's two versions of this chip. One with a single dac, and one with two of them. The LDAC pin and the buffers allow you to write data to both dacs, and then have them output the right voltages simultaneously. If the input were not buffered the first dac would start outputting before the second got the new data.
With a single dac, I'm not sure what the point of the buffer being there is. Maybe they just didn't want to design a whole different chip. Or maybe it's to allow more precise timing of when the output changes. I dunno.
I guess all I need to know now is how the DAC can output 2x the input voltage. I think this hase something to do with the voltage reference and VCC being different. Hm... Is that a voltage divider on pin 6 in the wave shield schematic?
Hm... it would appear that resistor and capacitor on the DAC's reference pin are actually a low pass filter:
Scroll halfway down that page.
Why would Ladyada have put a low pass filter on the voltage reference pin of the DAC? I thought the voltage reference pin was supposed to be whatever voltage you wanted the dac to output at most?
[edit]
Okay, I'm completely lost with the mathematics of how to calculate exactly what that low pass filter is doing to the voltage reference. It wants an imaginary number and the radian frequency of the input voltage. I have no idea what those are.
[edit]
Hm... maybe it's not a voltage divider at all, and that is simply a bypass capacitor to reduce noise on the voltage reference line. But why the 100K resistor on the voltage reference then?
maybe it's not a voltage divider at all, and that is simply a bypass capacitor to reduce noise on the voltage reference line.
Yes that's it.
It wants an imaginary number and the radian frequency of the input voltage.
In electronics an imaginary number is one that is on the Y axis and represents a phase shift of 90 degrees.
Radian frequency is simply 2pi f
With a single dac, I'm not sure what the point of the buffer being there is.
So you can load it in any time before the next sample is due but not output that sample until a clock pulse.
I guess all I need to know now is how the DAC can output 2x the input voltage.
It can only do this if the reference voltage is at least half the supply voltage to the chip. This also applies if the chip is being supplied by split power rails. That is a positive and negative voltage, then if the reference voltage is 4 volts then the output can go from -4v to +4V.
What's the 100K resistor on the voltage reference line for though? Is there a need to control the amount of current flowing into the voltage reference pin?
Anyone? I need to know if that 100K resistor is needed before I can wire up any prototype lest I potentially blow up my chip and I can't find anyhting in the dac datasheet exlaining why it might be there.
I saw someone mention in another thread the the Arduino's SPI was 8-bit and that if you needed to interface with a 16-bit device you would need to resort to bit-banging.
I wasn't sure if this was true or not, but I got back to reading the datasheet for my DAC again, and I found this on page 18:
All writes to the MCP492X are 16-bit words. Any
clocks past 16 will be ignored. The most significant
four bits are configuration bits. The remaining 12 bits
are data bits. No data can be transferred into the
device with CS high. This transfer will only occur if 16
clocks have been transferred into the device. If the rising
edge of CS occurs prior, shifting of data into the
input registers will be aborted.
Does this mean what I think it means? That if I write a byte to the dac, when the CS pin goes high after the write occurs, the DAc will simply toss out that data and start fresh with the next byte I attempt to send, preventing me from ever sending the 16 bits required to actually cause it to change the output voltage?
Grumpy... I think you might have been mistaken about that capacitor/resistor on the voltage reserence pin that I asked about. I just found this on the waveshield page:
The DAC also has a Vref input, this is the reference voltage that it uses to define the maximum analog value it can generate. There is a very low low-pass filter connected to it (C6 and R8) so that any digital noise (there is -a lot-) will not make it into the audio signal.
So it is a low pass filter.
[edit]
Well maybe you weren't mistaken. Maybe I just didn't explain what I was asking well enough. The wikipedia voltage divider page I linked to showed that type of resisotr capacitor combination and seemed to indicate it was both a voltage divider and low pass filter. So when you said it wasn't a voltage divider, I assumed you meant it also wasn't a low pass filter.
I guess though that those tiny bypass caps must be low pass filters. But I haven't seen them used with resistors like that before...
Firefox didn't copy when I hit ctrl-c. It does that sometimes. I fixed the link.
