The layout isn't great I'm afraid, huge loop areas and no ground-plane. With fast logic its important all signals have a close-by return path - which is why ground-planes are very useful, each signal has a return path underneath it. With single-sided PCBs you have to be pro-active in adding lots of ground traces to allow return paths to be as tight as possible - a ground-fill and some wire links is often needed to get a good layout. Poor layout doesn't mean the circuit won't work, but if it doesn't work its a strong suspect.
Large loops have lots of inductance which is bad news for fast signals, especially clocks with nanosecond rise- and fall-times. This also implies that on single-sided boards the power and ground should run alongside each other, just as they should come into the board on a twisted pair of wires, not separate wires.
The decoupling caps need to be close to each and every chip, with short leads as possible. The value is not critical, anything from 100nF to 1uF MLCC will probably work well for most discrete logic chips like this (unless the datasheet says otherwise).
Yes, it does get warm. The current through 7805 is 200-250 mA so it gets warm for sure.
Apparently, it remains the same. Interesting observation: When I use the DMM to measure the voltage across one of the cap nears 74595, I find that I get the correct outputs on the display. I think it's because of the internal battery of the DMM helps the capacitor stabilize the voltage
The 9V also remains mostly the same with variation of 0.1-0.2V.
Changes to capacitors:
7805 input cap is now: 220nF + 100nF = 320 nF (recommended is 330nF)
7805 output cap is now: 100nF (recommended is 100nF)
I also changed the cap placements to make the wires short.
I changed the 7805 caps to the recommended values but it still does the same.
7805 caps:
input side: 2 caps in parallel making 220 +100 = 320nF (recommended is 330nF)
output side: 100nF (recommended is 100nF)
It still does not work
I think you have identified the problem correctly but the solutions don't seem to be working
Its not voltage from the DMM, when in DCVolts range the only potential on the meter probes is from the supply you are measuring.
When I use the DMM to measure the voltage across one of the cap nears 74595,
Replace that capacitor and add a few more.
It sounds like with long tracks the supply is full of switching glitches the AC impedance of the meter is enough to suppress them, but I suspect a gnd loop or inadequate ground tracks.
Shorten the leads on the bypass caps you have fitted, make the cap straddle the EVERY IC, long leads can also lead (pun intended) to problems.
Other than that, place copper wire along your power tracks to the ICs and solder them in place to add to the cross-section of conductor.
ESPECIALLY your GND tracks, if it snakes around the place there is another possibility of problems.
Can you post a picture of the other side of your PCB please?
Yes, I know the layout is not the best. I am trying to keep it simple for the prototype. A lot of people have suggested decoupling caps for 7805 and vin of shift registers. Would I need something for clk signals given the long traces?
Hi,
Thanks for the pics.
If I trace your gnd correctly it snakes around parallel to your clock and data tracks.
This gnd track is also carrying display power current.
Can I suggest you cut free from those gnd tracks and hard wire the gnds over the PCB.
FWIW, the PCB is already laid out fairly well. Power, ground and signal lines are travelling together from one section to the next, as they should be. Your suggestion would introduce large inductive loops in the ground return!
Which is DC. Only ever a single transient when the latch is triggered. It is certainly the case that the 12 V should also be routed in proximity to the other lines but It seems rather improbable that this in itself would be the culprit. And note that the LEDs all have series resistors, damping any inductive transients. If anything, I would go with running sturdier wire on top of the ground tracks which clearly have been incorrectly specified and laid out - they should be at least four or five times as wide wherever possible (which considering the available board area, is everywhere ).
Disregard where previously I thought level shifting as the the number one concern, as I have a new one here ...
I've previously used 7805s in an application where its input was 12V. This limited the max current output at 5V to about 110mA. You're using 9V, so the max current will be somewhat higher, but I suspect you're hitting the thermal shutdown limit and the partial shutdown at 5V isn't being picked up by the multi-meter (an oscilloscope would reveal this).
try reducing the 9V input of the 7805 to about 7.8V by connecting two 1A diodes (i.e. 1N4004 to 1N4007) in series and add a 1µ to 10µF capacitor from 7.8V to GND. Having 7.8V at the input will boost the 7805's max current substantially as opposed to using 9V.
try using a 7.5V dc power supply for the input to the 7805
You can have a ground plane on a 1-layer PCB. It's just a large "pour" that covers all the blank space. Traces are run through channels (the pour just clears any traces). Now you can just jumper to the pour anywhere on the board and have a low impedance ground. Sometimes layout considerations will necessitate wire jumpers to cross over the pour, but it's a small price to pay for decent EM performance.
There are many problems with a direct connection between different logic families. I suggest you research it to gain a comprehensive understanding, rather than be told here.
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