Am I correct to say that this does not need an external pull down resistor as well ?
The pin will only occasionally be HIGH for about 5 minutes at a time.
When the ATMEGA chip resets it sets all I/O pins to input and engages all internal pull_up resistors. So it's not defined as output. I guess pull-down resistors are useful at that moment to output LOW. Hope others confirm this. I've never done this.
One frequent useful application for a external pull-down resistor is when controlling a logic level N-channel MOSFET that is switching an independent load and voltage source. The pull-down resistor will ensure that the mosfet is forced off if the arduino was powered off but the external switched load voltage source is still hot.
And yes, the powerup or reset default for I/O pins is input mode, internal pull-ups disabled.
And yes, the powerup or reset default for I/O pins is input mode, internal pull-ups disabled.
I agree, the datasheet states that rather clearly. I just don't understand why (1) people make unsubstantiated statements about the device characteristics, and (2) why others blindly believe them.
Update: sorry for the attitude, I'm apparently missing something. Searched the internet and still can't find where it says atmega328 disables pull-up at reset.
OK here it is something on page 8.The Port B(and etc.) pins are tri-stated when a reset condition becomes active, even if the clock is not running. That's all. Searched pull-up through the doc and nowhere mentioned where the tri-state is also coupled with enabled pull-up or not at reset.
So I'm wrong to say pull-ups are enabled at reset.
floresta, if you're so confident you're right why don't YOU go back to the spec sheet and point out where it says pull-ups are disabled at reset? It's not anywhere after searching through it myself. So maybe I just don't have your quality to see it. By not pointing out the "obvious", you're no better than anyone making mistakes, as you don't point out where the right answer is, which is what you hold against me.
Just show me and could you stop blaming me twice or more for one mistake?
floresta, if you're so confident you're right why don't YOU go back to the spec sheet and point out where it says pull-ups are disabled at reset?
You already did it for me, but the first clue is actually at the very beginning of section 13.2 where it says that "The ports are bi-directional I/O ports with optional internal pull-ups." If pull-ups are optional then they are not enabled by default. If the pull-ups are enabled by default then the ports are optionally floating.
The definitive statement is the one in section 13.2.1 that you pointed out: "The port pins are tri-stated when reset condition becomes active...." If a pin is tri-stated it is by definition pulled neither high nor low. That's all you need - the pull-up is not enabled - period.
nowhere mentioned where the tri-state is also coupled with enabled pull-up or not at reset.
It won't be mentioned because the two emphasized terms are mutually exclusive. Tri-state means high impedance which makes the level indeterminate, not high and not low.
Just show me and could you stop blaming me twice or more for one mistake?
All I said was: "Are you sure about this?" I didn't blame you for anything, I had my opinion and I wanted to find out if I had overlooked something.
Don
And now for some trivia. If I remember correctly the term 'tri-state' is specific to one manufacturer and the correct generic term is 'three-state' (I may have this backwards). This is not unlike the current situation with 'I2C' and 'TWI'.
And now for some trivia. If I remember correctly the term 'tri-state' is specific to one manufacturer and the correct generic term is 'three-state' (I may have this backwards). This is not unlike the current situation with 'I2C' and 'TWI'.
Thank you floresta. I'm sorry for my attitude. After some searching, I realized tri-stated means the same as High-Z but still it's the property of the gate. The pull-up resistor seems to me to be "not a part of the tri-state gate". P77 is the diagram of a pin. I'll study it more.
liudr:
Thank you floresta. I'm sorry for my attitude. After some searching, I realized tri-stated means the same as High-Z but still it's the property of the gate. The pull-up resistor seems to me to be "not a part of the tri-state gate". P77 is the diagram of a pin. I'll study it more.
"Tri-state" defines a possible enabled state of a digital output pin, not an input pin. Some output types are open collector, open drain, TTL output and TTL Tri-state. Each is electrically different. The output pins on an arduino are not strictly defined as Tri-state output pins as there is no way to have the pin enabled as an output pin and still be in a tri-state mode. Once you use the mode statement to set a pin to output, it will immediately assume either a active high or active low state. Only by redefining the pin as an input pin with the mode statement will the pin assume a Hi-Z mode, assuming the internal pull-up is not enabled. An Arduino I/O pin can be made to mimic a tri-state output but only by changing it's mode from output to input and then back to output depending on what state you need it to be placed in. This is seem in the popular Charlieplexing scanning technique.