Impedance of pins 20 and 21 on Mega 2560

Projects General Guidance
1

I am proposing to use a Mega 2560 to detect when a number of LDRs are in shadow. In my initial tests I was not using pins 20 and 21 (which are also SDA and SCL) and everything is working fine. I have a 220k resistor connected to VCC and to the LDR and the other end of the LDR connected to GND. When the light falls on the LDR it registers LOW at the junction between it and the resistor. When it is in shadow it registers HIGH.

But when I connected two LDRs to pins 20 and 21 they registered "dark" unless I shone a very bright light on the LDR. It is behaving as if those pins present a very low impedance.

I have tried both a genuine Mega and a clone with the same result.

Normally for detecting the LDRs I have the I/O pin set as INPUT but it made no difference to pins 20 and 21 when I applied INPUT_PULLUP.

I have not been able to find anything in the Atmega datasheet to suggest that those pins behave differently from any other I/O pin.

It is a real PITA if I can't use those pins because I had a very convenient pin allocation worked out - I have about 20 LDRs to work with.

Is anyone aware of any reason for this behaviour or a workaround?

...R

2

It would be interesting to see if the problem manifests itself on an Uno using the A4 and A5 (alias 18 and 19) pins, to see if it's I2C related.

3

Willpatel_Kendmirez:
It would be interesting to see if the problem manifests itself on an Uno using the A4 and A5 (alias 18 and 19) pins, to see if it's I2C related.

Feel free :slight_smile:

...R

4

The official schematic shows 10K pullups on SCL and SDA. Trivial to remove.

5

jremington:
The official schematic shows 10K pullups on SCL and SDA. Trivial to remove.

Thanks. That explains things. It's very small so I had not noticed it on the board.

I don't want to modify my Mega so I will have to re-allocate my I/O pins. Bugger.

...R