# In the ADC why is the sample-and-hold capacitor connected to Vcc/2?

From the datasheet for the Atmega328P, in the ADC input circuit the sample-and-hold capacitor (14 pF) is connected to Vcc/2. Why that and not ground?

My guess* is that this allows for a faster charging time. With a 5V input (and assuming Vcc is 5V) then the capacitor only has to charge up to 2.5V (being 2.5V over Vcc/2). And with a 0V input the capacitor charges (negatively) to -2.5V.

Or is there another reason?

• Which I am starting to think is nonsense.

Ist that the cap that makes the "and hold" part of the sample and hold input to the ADC?

Yes, it supposedly holds the input value, while it is being tested. This lets the value (on the input pin) change during the (nominal) 104 µs that the conversion takes.

My other guess is - bearing in mind that capacitors are hard to implement on printed circuits because of the space they take - that they only need to make a 2.5V capacitor rather than a 5V capacitor. Presumably it can be smaller.

The atmega uses an SAR convertor.
The first ‘guess’ it makes is VCC/2 then higher / lower.

So if looking for a particular voltage (comparator) , making it midrange should make the conversion faster.(i think).

Or more accurate perhaps, ill look it up later.

Its conversion time.

EDIT

Starting with the MSB gives VCC/2, subsequently lower bits gives the minimum no of comparisons to reach 1 LSB value.

There are other variations but this is the most common.

The settling time of the DAC is greatest for the most significant bits, so starting in the middle reduces the total settling time on average.

I will try to qualify that later.

Hi, The maximum magnitude you have to charge the cap is 2/Vcc so faster than a cap that is at gnd, and needs to charge to Vcc at times.

Tom... :) I think we are all correct in one way or another.

The maximum magnitude you have to charge the cap is 2/Vcc so faster than a cap that is at gnd, and needs to charge to Vcc at times.

Yes, but the time to charge a capacitor to 99.33% is 5τ (where τ is R*C). The voltage is not part of the equation.

Boardburner2: The settling time of the DAC is greatest for the most significant bits, so starting in the middle reduces the total settling time on average.

The sample-and-hold capacitor charges to a certain voltage and holds it. I don't see how that reduces the settling time. If we have a 5V input the sum of 2.5V on the cap, and 2.5V (being Vcc/2) will be 5V. I don't see how that changes the settling time.

The sample-and-hold capacitor charges to a certain voltage and holds it. I don't see how that reduces the settling time. If we have a 5V input the sum of 2.5V on the cap, and 2.5V (being Vcc/2) will be 5V. I don't see how that changes the settling time.

[/quote] Successive comparisons require the output of the DAC to settle before comparing it with the value on the sample hold, the MSB has the longest settling time which dictates the max rate of conversion per bit.

I realise i have worded badly and have edited earlier post.

And im not making much sense now either.

Need sleep i ll have another go later.

TomGeorge: Hi, The maximum magnitude you have to charge the cap is 2/Vcc so faster than a cap that is at gnd, and needs to charge to Vcc at times.

Not true at all, if one pin is at 0V and the next at 5V the cap has to charge 5V when the multiplexer switches from one pin to the next. The fact it changes from -2.5V to +2.5V rather than from 0V to 5V is not significant, it still have to slew 5V. Even if the other end of the cap were at 20V it makes no difference to the charge flow. change is charge is directly related to change in voltage.

The precise answer to this question lies in the mind of the Atmel engineer who put together the ADC design which is Atmel proprietry IP and they won't be telling anyone the full design rationale! Its probably a fairly standard SAR ADC design anyway, they probably all do this.

Its certainly the case that referencing the capacitor at midrail makes capacitor leakage unbiased w.r.t. the voltage rails. Balanced circuits usually outperform singled-ended ones.

Wow…good catch. I can say for certain that SAR ADC diagrams in datasheets usually do show their S/H caps to ground. I didn’t notice that this one went to Vcc/2 (which I imagine is actually Vref/2).

I’d guess speed personally. Yes, you have to wait a few time constants to get the last bit of the conversion. If you were charging a S/H cap to Gnd, then you’d have to wait 1 time constant just to start converting the 1st bit. But if you are charging a S/H cap to Vref/2, then immediately after starting the sample you’d know what the 1st bit is by whether the S/H voltage is getting pulled up or down.

I can’t say that I make ADCs for a living, however I work with people who do so I might ask them about this tomorrow. I wonder if this isn’t a trick that all SARs use, whether their datasheet shows the S/H cap to Gnd or Vref/2. I know that when I previously experimented to understand these diagrams in other micro datasheets, I got results that were only explained if their diagrams were too simplified to tell the whole story.

MarkT: Not true at all, if one pin is at 0V and the next at 5V the cap has to charge 5V when the multiplexer switches from one pin to the next. The fact it changes from -2.5V to +2.5V rather than from 0V to 5V is not significant, it still have to slew 5V. Even if the other end of the cap were at 20V it makes no difference to the charge flow. change is charge is directly related to change in voltage.

The precise answer to this question lies in the mind of the Atmel engineer who put together the ADC design which is Atmel proprietry IP and they won't be telling anyone the full design rationale! Its probably a fairly standard SAR ADC design anyway, they probably all do this.

Its certainly the case that referencing the capacitor at midrail makes capacitor leakage unbiased w.r.t. the voltage rails. Balanced circuits usually outperform singled-ended ones.

Hmm...yes, good point. I hadn't considered the cap being previously charged from a previous conversion.

It's possible that the AVR SAR resets its S/H in between conversions. My experience with other microcontrollers has been that this is not done, but they don't show their S/H caps referenced to Vref/2 either.

Have people verified that AVR ADC samples are affected by the previous samples if they try to sample too quickly?

"Have people verified that AVR ADC samples are affected by the previous samples if they try to sample too quickly?"

Yes, you will see plenty of posts where it is recommended to read the same channel twice to give the channel time to settle before moving on to the next one, especially when the source impedance is > 10K.

I thought that was because the switch to the next input hadn't begun by the time you raised the "start conversion" flag. The ADC runs on its own clock that is asynchronous to the main clock. You can ask it do do something but it doesn't do so immediately.

CrossRoads: "Have people verified that AVR ADC samples are affected by the previous samples if they try to sample too quickly?"

Yes, you will see plenty of posts where it is recommended to read the same channel twice to give the channel time to settle before moving on to the next one, especially when the source impedance is > 10K.

I see. Well, that certainly proves it.

I'll ask a SAR engineer tomorrow if he knows why Atmel's S/H would be referenced from Vcc/2.

BigBobby:
Wow…good catch. I can say for certain that SAR ADC diagrams in datasheets usually do show their S/H caps to ground. I didn’t notice that this one went to Vcc/2 (which I imagine is actually Vref/2).

Yes, I wonder if that is a typo.

So far my main theories are:

• You can make a smaller cap (ie. 2.5V 14 pF rather than 5V 14 pF) on the die
• Being a smaller voltage in the cap it would leak more slowly?

BigBobby:
I’ll ask a SAR engineer tomorrow if he knows why Atmel’s S/H would be referenced from Vcc/2.

Or if indeed it is actually Vref/2? Sounds good.

MarkT: The precise answer to this question lies in the mind of the Atmel engineer who put together the ADC design which is Atmel proprietry IP and they won't be telling anyone the full design rationale! Its probably a fairly standard SAR ADC design anyway, they probably all do this.

And in my reference book , which i cannot find.

This came up in a term paper i think decades ago, my notes are unclear , related i think to 2 stage converters at the time.

Im sure it was speed/accuracy related.

Be nice if its a typo though. :confused:

EDIT It was this book i think if anyone has a copy. http://www.amazon.com/Analog-Digital-Conversion-Handbook-Technical-Handbooks/dp/0130328480

[quote author=Nick Gammon link=msg=2704286 date=1460262855] My other guess is - bearing in mind that capacitors are hard to implement on printed circuits because of the space they take - that they only need to make a 2.5V capacitor rather than a 5V capacitor. Presumably it can be smaller. [/quote]

Its possible to make up to 100 pF or thereabouts.

With junction caps the capacitance varies with voltage however.

Not sure this applies to mos though.

I wonder if it's one single cap, or several combined junction caps to VCC and VDD. A 7pf cap to VCC and a 7pf cap to VDD can be seen as a 14pf cap to some virtual point in the middle. Leo..