Increasing PWM Frequency for FET Gate Drive

I am working on a project involving using, preferably, an ATTiny to drive the gates of FETs. The FETs will be used in the creation of a DC-DC converter. The problem that I don't know how to solve is how to effectively increase the PWM frequency of the controller. The frequency I need is anything greater than 400kHz. Any suggestions?

400kHz is rather a high frequency to use for a DC-DC converter, apart from ones that handle very small amounts of power. Are you sure you need such a high frequency?

If you clock the timer that is providing the PWM from a 16MHz system clock, or from a 8MHz clock if you are using the internal RC oscillator, then you can get a PWM frequency of 500kHz using a divisor of 32 or 16 respectively. But then you will have only a few bits of PWM resolution. However, timer 1 on the attiny25/45/85 can be clocked from the fast peripheral clock, which you can set to run at 64MHz or 32MHz. Using 64MHz, you could set the divisor (i.e. TOP value) to 128, giving 500kHz with 7-bit PWM resolution, if my reading of the datasheet is correct. See the datasheet for more details.

You will have to use FET gate driver chips to drive the mosfets at those frequencies.


Not long after I posted this thread I also found the PCK section of the data sheet. I assume all of the control registers can be properly changed using the arduino environment? Is it possible to print the contents of registers via Serial.println?

The high frequency is due to the desire to decrease the required component sizing. I am working on a ZETA converter that, at 400kHz, could use single ceramic capacitors rather than many in parallel for a 32kHz configuration.

Thanks again for the reply dc42

What FETs are you using, in particular you need to consider the gate
charging and discharging times and the level of gate drive current
needed. The more gate capacitance and switching speed needed the
more gate drive is required. At 500kHz you need very fast switching
indeed (even 50ns rise/fall times will lead to noticeable switching loss).

Optimizing such a circuit means paying careful attention to all the losses,
which include DC losses, switching losses, gate-driver losses and inductor
losses. There are various application notes from manufacturers out there
on the web about this if you have a look around.

Hey Mark,

Thanks for the tips, for the most part I have been taking into account all of these aspects. We decided to go with EPC GaN FET's and the TI LM5113 to drive them. As I understand, FET's don't really get much better than these. I haven't directly determined switching losses, though I do know that they increase with switching frequency. I think that switching losses typically increase linearly with switching frequency. From a first level analysis, the inductor DC resistance losses account for the large majority of the converter power dissipation. Since the switching frequency decreases the size of the inductor needed however, the inductor losses can be decreased dramatically. Though, again, I haven't directly included switching losses in the overall efficiency calculation.

Ah, those GaN FETs.... Wondering about playing with them, they have superior
characteristics to silicon (apart from voltage handling!) and in particular low