The analogue inputs are a high resistance, and will draw very little current.
The sample and hold circuit, which determines which of the six analogue inputs is connected to the single analogue to digital converter, at any one time is optimised for use with analogue circuits with an output impedance of 10kΩ or less. The 2.2kΩ you have seen on a circuit diagram will ensure that this condition is met.
See section 23 of the ATmega328P Datasheet for more details.
23.6.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 23-8. An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless
of whether that channel is selected as input for the ADC. When the channel is selected, the
source must drive the S/H capacitor through the series resistance (combined resistance in the
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.