Numbers for the UNO R4 analog input

[DrN]

Following is some analysis for the analog input of the UNO R4. The analysis is very general, you can plug numbers for whatever board you like.

First, as always, start with the datasheet. Here are two snapshots from the RA4M1 datasheet pages 87 and 88. The first shows the clock and input impedance, the second shows the sampling time.

To help us understand what this means for our voltage measurements, here is an equivalent circuit for the part of the analog input that samples the input voltage.

Notice we have a 2.5K ohm resistor in series with the 8pF switched sampling capacitor. The time constant is of course 20 nsecs.

So how does that compare to the sampling time? The datasheet lists the conversion time as 800nsecs, and in footnote 1 it says this includes the sampling and comparison time. The clock is 64MHZ. So that probably means conversion takes14bits/64Mhz = 218 nsecs and the budget for the capacitor to charge to the input voltage is 600 nsecs.

To get an accurate reading using this input, we need that within this sampling time, the capacitor is able to charge up to within 1/2^14 of the input voltage. One part in 2^14 is 1/16,384. That is pretty small. How long will it take?

The voltage on the capacitor after some time t, is

For 14 bit resolution we want

or equivalently,

In other words we need about 10 times the RC time constant, or 200 nsecs. The chip seems to give us 600nsecs. So far, so good.

Now what happens when we add a large series resistance in front of the analog input? The data sheet recommends something like 300 ohms as a max. But let's see what really is if those numbers are right.

We know that we need 10 x RC for 14 bits. So, how much R can we have? Well that's easy, it's

So the max resistance we can put in series between the input and wherever the current comes from, is 60nsecs/8pF ~ 7.5K. The internal 2.5K resistor leaves 5K of resistance to just squeak by for 14 bits.

One last thing, pro-forma. We should ask whether the 8pF capacitor is big enough for 14 bits of precision.

A switched capacitor network has a voltage noise as least as big as

Notice that noise gets bigger when the capacitor is smaller.

For our 8pF sampling capacitor at a temperature 20C, the voltage noise works out to 21.5uV.

(Use k=8.6x10^-5 eV/T(K), T = 20C+273.15K = 293.15K and C=8pF (columbs/V) x 6.8 x 10^18 e/c)

So, how does that compare to 1 LSB with a 14 bit input, lets say with a 5V range?
Well 5V/ 2^14 is about 300uV. So we're pretty safe with that capacitor. The resistor noise for 10K is also much smaller, less than 10uV in the 100kHZ range.

Notice the manufacturer lists the quantization error as 0.5LSB, and typical overall accuracy as 1.25LSB. It seems like we should be able to get that with just a little bit of care.

[westfw]

Shouldn't the 2.5k resistor in your pseudo-schematic go to ground?

It's been pointed out before that the low input impedance of the R4, compared to the AVRs, could be a significant problem...

[DrN]

It seems most likely that the 2.5K is in series with the sampling capacitor.

That is a common topology in the analog inputs of MCU's.

It is not correct nor ideal.

It is a cheap way to reduce the kickback for those who do not know how to connect to a SAR.

It comes at the expense of a longer sampling window and preempting being able to drive it in a more correct way (with an opamp and RC to act as charge reservoir).

[westfw]

@DrN

It seems most likely that the 2.5K is in series with the sampling capacitor.

But it would not result in an input impedance of only 2.5k, would it?
I mean, the ATmega328 datasheet shows almost exactly that schematic, but lists a very high "Analog Input Resistance"

[DrN]

The ATmeta328 datasheet lists 10 bits referenced to 1.1V, sample and hold seems to be 2 1/2 clocks for the first and 1 1/2 clocks after that, the conversion circuit requires that the clock be between 50kHz and 200kHz, and they list 65 to 260us conversion time.

So let's see how it adds up.

From the reference voltage and number of bits, we are looking for precision of 1.1v / 2^10 = 1mV

Noise for a switched capacitor sampling network is

v_n = 3.6x10^-6 x sqrt[ T(kelvin)/C(pf) ].

At room temperature, approximately 300K and 14pF sampling capacitor, v_n is about 16 uV.

So far so good. Let's look at the sample and hold time.

Time to charge up the capacitor to within 1 part in 1,000 in terms of the RC time constant, is

t/RC ~ -ln(1/1000) ~ 7.

So we need a sampling time that is 7 times the RC to charge up the capacitor.

For the low resistor we have RC = 1K x 14pF = 14nsecs. Therefore it takes 100nsecs for the capacitor to charge up with in 1/1000 of the applied voltage.

Now since the sample hold runs in 1.5 clock cycles, the fastest we can run the clock is 1.5 clocks/100nsecs = 15MHz. The conversion circuit needs 50KHz to 200KHz, so we're fine with that.

If we consider the large resistor, 100K, then the RC is 1.4usecs and input needs 10usecs to charge up to 10 bit precision. That means we need to set the clock speed to less than 1.5clocks/10usecs = 150kHz. So now we need to be a little more careful in selecting the clock for the ADC. We have to make sure we stay below that.

Now, if you connect this to a high impedance source, say a 10K+10K divider network with a thermistor as one of the resistors, then for the 100K input it won't change things by very much. But it does make a difference for the 1K input.

It would be a good exercise to calculate the sampling time needed for the case of a 10K+10K divider with the middle tap connected to the analog input with the 1K and with the 100K internal resistor.

[johnerrington]

Thats an excellent analysis.
Poor wording in the data sheets has led to a misconception among newbies that the "ACTUAL" input resistance is low.
As you say "analog input resitance" is the value of the SERIES resistance and is relevant only to sampling time.
I made a simple measurement of the REAL input resistance for a NANO like this

even for a well used board plugged into a breadboard the 300Mohm series resistor did not prejudice the measurement value. Results were still within the spec for the ADC - 1LSB

(I oversampled 1024 times then did a statistical analysis on a set of 120 readings)

My test suggests the actual input resistance is hundreds of GOhms.

So unless you are making very fast measurements you DONT need to stick slavishly to the "optimised for an Rin of 20k"

[westfw]

@johnerrington

As you say "analog input resitance" is the value of the SERIES resistance and is relevant only to sampling time.

Are you sure? People have had results with the R4 that are inconsistent with that.
(although I guess that could be bugs in the code, too...)

[johnerrington]

I dont have an R4 to test; however an ADC that changes the voltage it measures, unless the source resistance is zero, would be ridiculous.

[DrN]

@johnerrington and @westfw

I can think of two ways to see the value of the internal resistor. One is put a comparable sized series resistor and a good voltage source in front of it, and use an oscilloscope and watch it charge up on a usec scale.

Another is to use an external series resistor, set a known ADC clock speed and keep increasing the external series resistor until you see the voltage deviate from the correct value. Something like what you did.

Graph, and fit to an exponential to obtain the "true" R for the RC assuming it is really 14pF for C. There should be a constant offset from your external resistor. If it never deviates from the correct voltage, then the schematic is not correct.

Here is an LTspice model for the sample and hold circuit, as depicted and connected to a voltage divider such as you might have with a 10K thermistor. The input is set for 100K series resistor and 5usec sample and hold.

Red is the tap on the divider, green is the SAR cap, and blue is the sample and hold clock. The red of course is what you should see if looked at the divider tap with an oscilloscope. The green trace shows a solid miss on the voltage at the sampling capacitor.

Adjust the clock that runs the switch to match your sample and hold time, and adjust resistor to taste.

Remember that you need that the voltage matches the true value within 1mV. When you think it is close, you will have to zoom in to see whether there is an error.

UNOR3_SAR_voltagesource_thermistor10K.asc.zip (826 Bytes)

[DrN]

@johnerrington

I dont have an R4 to test; however an ADC that changes the voltage it measures, unless the source resistance is zero, would be ridiculous.

By "change the voltage it measures" you mean that the measurement produces a reading different from the voltage at the input?

That is what any ADC does when not used correctly. The SAR is famous for it. But pretty much every ADC has a sampling capacitor.

The SAR is also famous for changing the voltage in the thing you are measuring. This is a large spike and it is called kickback. It can even makes it way to the input side of an opamp buffer.

Again, kickback is a result of misuse.

Those resistor built into the analog inputs my many MCU's are a cheap way to tame kickback. They let hobbyist get away with a certain amount of misuse. But they also preempt any possibility of using the SAR correctly.

There is a lot of detailed information available in application notes.

Search for "SAR kickback" and for "driving a SAR" in application notes by professionals at TI, Analog, Microchip etc.

Again, the best you can do with the analog input of an MCU is put an opamp buffer in front of it. That can give you a high impedance input and a low impedance source for the analog input.

[johnerrington]

@DrN

By "change the voltage it measures" you mean that the measurement produces a reading different from the voltage at the input?

No. Please credit me with some intelligence, as I do for you.
I have a 50 year background in electronics and taught at UNI for 20 years.

By its nature an ADC changes an analog reading to a number.

Here is a typical example of a measurement one might wish to make.

Measure the voltage with a 'scope: you see 4.75V
Measure it with an ADC that has an input impedance of 50k // 20pf you see 2.5V.

The action of connecting the 'scope or ADC to take the reading has changed the actual voltage at the point of measurement. (OHMS LAW).

I see where you are coming from; this video assumes the internal capacitor is initially fully discharged, and the input is equal to Vref.

However in the context of measuring the shape of a changing signal that is nonsense. For the reading to have any useful meaning the input must have changed little between one measurement and the next, in which case the value of "kickback" will be small.

@DrN

One is put a comparable sized series resistor and a good voltage source in front of it, and use an oscilloscope and watch it charge up on a usec scale.

And allow for the input impedance of the oscilloscope? Its a common misconception that you can just "connect a 'scope" without changing the value being measured.

Can I ask why in your simulation you have a switch discharging the cap to ground?

The usual SA ADC circuit has no such switch that I can see, and the usual block diagram would indicate as would be rational that the SH cap would retain its charge from one reading to the next, following the principle that the most likely new voltage will be little different to the previous one.

mt-021.pdf

[GolamMostafa]

@johnerrington

as would be rational that the SH cap would retain its charge from one reading to the next,

I have thought that the holding capacitor is discharged before the next sample of the input signal. If not, how would it detcet the presence of a sudden noise on the input signal?

[DrN]

That's wonderful, I appreciate that.

First, I think your prediction that the 50K/20pf input sees 5V, has two assumptions, a) that the resistor is in parallel with the capacitor, i.e. goes to ground and (b) that the capacitor is not discharged between readings. Presumably the model you have in mind is that the switch comes between the resistor and the capacitor.

First, let's please check those assumptions, and of course with apologies, I do want to be respectful (it is important, even if I might actually be a little older and also was on faculty).

a) The topology for MCU analog inputs.

The trend in MCU manufacturers is to put a resistor in series with the switched capacitor. Here are examples from datasheets of the parts we have been discussing in this and another topic.

The Atm328p datasheet,

The NXP IMXRT1060 datasheet,

The Renesas RA4M1 group datasheet

Note that these are not bare SAR inputs. They all have that resistor in series with the sampling capacitor. I did find one example where they do not build the resistor into the input, I think it was by Microchip (Their AE just got back to me.)

The reason they do that, I believe, is to tame the kickback. (Here is an app note on kickback, a well known phenomenon of SAR inputs. Analog Basics—Part 5: Tackling Difficult Input Driving Issues for the SAR ADC)

The hobbyists who buy these boards (and professionals who want to skimp on parts) insist on hooking these inputs to high impedance sources (or whatever they think they can get away with). That resistor is the cheap way to handle it, it at least reduces the kickback at the cost of needing a longer sampling time.

A better solution would be to put an opamp buffer and RC in front of the SAR, as is normally done to drive a SAR. Here is an example from Designing SAR ADC Drive Circuirty (R. Downs, Texas Instruments)

Note that to include zero in the input range, he needs a negative rail, at least -0.3 to -0.7V if it is a rail to rail opamp.

I imagine that is part of why they go with the resistor rather than an opamp, in addition to space and cost.

b) Sampling capacitor holding charge or discharge

The Spice models that I use for the switched capacitor sampling network, is based on this publication by Analog, LTspice: Simulating SAR ADC Analog Inputs

Here is the figure showing their spice model for a SAR.

Notice that the capacitors are discharged at the end of the sampling cycle.

Leaving it charged at first seems to make sense, but then at some point you may be presenting a source at 0 volts to a cap that is already charged up to 10 volts, potentially a not nice situation.

Keep in mind also, that in a real SAR the cap may be a series of capacitors. The switch for the first one is the big sampling spike that propagate back through what you attached to it.

c) What do I read from the divider?

The answer is that when the switch closes the capacitor is at 0 volts and you get the effect of that series resistor in parallel with the lower leg of your divider. After the capacitor is charged up, it looks like a resistor tied to whatever voltage it got to, if fully charged then in effect it is like an infinite resistance in that no current is flowing.

So, the answer is:

The voltage seen in the conversion step is the voltage that the capacitor is able to charge up to within the sampling time.

This is the cardinal rule of pretty much all ADCS, in so far as the feature a sampling capacitor input.

If your sampling time is long enough, you read the correct voltage, approximately 5 volts. If your window is too short, you see something less than 5volts.

For proof, here is a spice model.

Notice the voltage starts at your 2.5V, but then rises towards 5V. In this instance the sampling window is too short, so it only gets to 4.6V

Now, I realize this is based on something that is not the assumption you built into your reply, that the resistor goes to ground (not like the equivalent circuits shown in the datasheets).

If the 50K really where to ground, then of course it would go from 0 to 2.5V, but that is not how the inputs are described in the datasheets.

I certainly invite you to try this on the bench with an oscilloscope and send us a picture. (it should look like the green trace, although you may have to play with part values and timing). If I find some spare time later, I might try it too. If the result is very different, then we have a good question to forward to the chip maker about their datasheet.

[DrN]

According to the app notes, it is normally discharged. And it makes sense. Who wants to connect to something that is holding a 10V charge.

But even it did hold charge, the name of the game is the voltage on the cap at the end of the sampling window.

So, as long as there is path for charge in or out to allow it to get to the right voltage in that time, you can get the right reading.

(The large series resistor messes that up a bit to tame the spike that appears in your external circuitry from passing all of that charge in a short time.)

[johnerrington]

@DrN

at some point you may be presenting a source at 0 volts to a cap that is already charged up to 10 volts, potentially a not nice situation.

Working on the premise that the most likely new value is not far from the previous value
(on which digital filtering is based) the least charge transfer would occur if the voltage on the sampling cap were not discharged between samples.

My test using a 300M resistor gave readings that were accurate to within 1LSB of the reading for a zero input resistance. I cant see how that would be the case if the sampling cap were discharged between readings.

@DrN

a resistor in series with the switched capacitor

thanks, yes I was aware of that, I was postulating the case that an ADC had a low input impedance (not the series resistance) which would prejudice any reading you made with it except on a zero impedance voltage source. (post #8)

@DrN

that is not how the inputs are described in the datasheets.

Yes, the wording is misleading. They mean the serial resistor on the input, not the total impedance at the input.

May I thank you for your responses, I'm still not too old to learn, and enjoy finding out new things about components I thought I understood.

[DrN]

@johnerrington

My test using a 300M resistor gave readings that were accurate to within 1LSB of the reading for a zero input resistance. I cant see how that would be the case if the sampling cap were discharged between readings.

Yes, this part I don't understand. It seems like you are comparing the two inputs, and find that the two give the same reading within 1LSB, yes? It seems a clever, simple test.

(For the readers, 300M is large enough that the charging time, for the voltage on the capacitor to rise from to within 1 LSB of the input, should take be much longer than the time afforded for sampling. RC = 300M x 14 pf = 4.2 msec, time to 1 lsb accuracy for 10 bits is -ln(1/2^10)/RC ~ 7, and 7 x RC ~ 50 msec. The longest sampling time afforded by that part is 1.5 cycles/50KHz = 30usecs.)

You wrote that you averaged for 1024 readings. What does the first reading look like?

If that shows something close to 0 for the 30M and yet averages to ~5V, then something is odd indeed.

(But, it just occurred to me, that perhaps they actually did design assuming discharge through the external circuit; it would save space, time and some tiny fraction of a penny by omitting the second switch. It all seems oddly consistent with marketing to hobbyists and cell phone manufacturers. More than that, it is frustrating that (for my use case, laboratory instrumentation) we cannot have an MCU with a sufficiently fast SPI nor a simple SAR).

[johnerrington]

Well, I did the test;

S(n) is an aggregate of 5 samples at 20usec intervals. Results from another test sampling at 50usec with no averaging are similar (but a bit more noise)
A6 measures V at the start and end of the test (agg * 64) - readings are 0 and 506
The expected final value would be about 506 * 5 = 2530

Interesting. It seems the cap is not discharged between readings.

I dont know where the 3kHz is coming from, it doesnt show on my Hantek 'scope.

Time constant: from the readings the value reaches 63% of full scale after 15 samples = 1.5msec. That would make Cin only a few pF. Even on a breadboard!

[westfw]

@johnerrington

S(n) is an aggregate of 5 samples at 20usec intervals.

Using analogRead()? Or are you directly accessing the ADC?

[johnerrington]

Thanks @westfw of course that explains why I'm seeing that frequency.
I'll change the code to use direct access. When I figure it out!

Changes the timing but doesnt cange the overall result.

[DrN]

Nice work. It looks like a charging curve, of course.

Perhaps the time scale could be set to t = sample number times SAR sampling window in seconds?

That should be the accumulated time the sampling cap sees the input. Hopefully it will look the expected RC time constant (500M x 14pf = 7.0msec).

For practical application, it means you look at your signal through an RC filter formed by the source + internal resistance and the capacitor in the sampling stage.

So that is an interesting approach by the manufacturers.