Nano every USB input voltage

Official Hardware Nano Family Nano Every
1

I am trying to understand the schematic of nano every(https://content.arduino.cc/assets/NANOEveryV3.0_sch.pdf).
On the USB input side, the D+/D- are directly connected to the PA24/PA25, with a PRTR5V to protect the ESD.

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According to the USB standard, the D+/D- are at 5V logic but the ATSAMD11D14A are running fully at 3.3V so the pin logic are also expect to be no more than 3.3+0.6V or it will damage it. (https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42363-SAM-D11_Datasheet.pdf)

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But in reality, I know all the nano every works, so how and where the magic of the level shifter happened?

On the other side, the connection of ATSAMD11D14A PA14/15, 22/23 are all using level shifter to 5V logic for the ATMEGA4809.

And also why the J2 pin 4 UPDI is connected to the 5V side of the signal instead of 3.3V logic at pin 11 (TX_UPDI) of ATSAMD11D14A? If the pin is connected there, the signal are still going to be level shifted to 5V, right? Or is that just the pin to program ATMEGA4809 even without power up the ATSAMD11D14A, so to match the voltage there, we have to connect to the 5V side?

I want to use one TXS0108E to do all the level shifter, both from the usb cable to the PA24/25 (2 channel) and from the ATSAMD11D14A to the ATMEGA4809 (3 channel) .
Is there any problem there?

Thanks

2

Maybe this will clarify?
By the way, D+/D- are 3.3V level.

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3

Where do you see this?

AFAIK the signal level specs are are 0.0–0.3 V for logical low, and 2.8–3.6 V for logical high level.

4

This is an image from USB hardware - Wikipedia about usb 2.0 voltage tolerance and limits.

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From there, I can see this is suppose to be 5V logic for USB standard.

5

You have cited an article about USB hardware, connectors, and power.

At the bottom of the Article you cite there is a link to USB Communications

In that Wiki article you will find

Electrical specification

USB signals are transmitted using differential signaling on a twisted-pair data cable with 90 Ω ± 15% characteristic impedance.[6]

  • Low speed (LS) and Full speed (FS) modes use a single data pair, labelled D+ and D−, in half-duplex. Transmitted signal levels are 0.0–0.3 V for logical low, and 2.8–3.6 V for logical high level. The signal lines are not terminated.
6

@cattledog Thank you for the link, yes, you are right.

Any comment on the level shifter? Will there be any problem to use TXS0104E instead of the discrete diode for the level shift for the 3 signal (TX, RX, UDPI)?

Thanks

7

For this part of the circuit, why use the MPM3610 and AP2112K-3.3? The circuit seems pretty complex.
How about LM3940 1A LDO?

8

I think the MPM3610 is to accept Vin up to 21V.
I'm not a hardware guy, and don't understand the differences in 5 -> 3.3v converters.

I would think that the chips used in the design of the Nano Every involved considerations of costs and availability at the time of the design.

9

Let’s see the difference between different regulators.

Suppose a board needs 50mA at 5V and it is supplied with 12V.

The UNO R3 uses the NCP1117, a linear regulator. It takes the same 50mA from the source, meaning a power consumption of 600mW of which 250mW is actually used and 350mW is heat loss.

The Nano Every uses the MPM3610, a switching regulator. The efficiency of this regulator is about 80%, meaning the power consumption of the board is 312mW, at a current of 39mA.

At higher voltages and/or higher currents the advantage of a switching regulator becomes more prominent.

10

@stitech Thank you!

11

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