Anti Hijack thread for specifically the use of an OV7670 (non FIFO) module on an arduino Due.
Continued from post #562
OV7670 mega and nano thread
EvIl_DeViL:
I updated my code with some of the suggestion stoney reported and indeed I got some improvements.
vsync edge detection is not influent in my case. I got the same image so I think it depends on how the code is written so for now I let it be as it was but I might consider changing this behavior accordingly to the code as it comes out. Thanks for pointing out and clarifying this issue.
I implemented HREF functionality but I couldn't get it working with interrupts; the same goes for PCLK so I needed to poll with a while loop (DAMN! :D)
I tryed to wait either for PCLK low and high before reading the pixel and I got these two versions; the first waiting for low as MrArduino did and the second waiting for high accordingly to my interpretation of the scheme I found on the DS which I post herein. (I'd go for the second version)
@stoney: why you think Hstart/Hend and Vstart/Vend are relevant? It's just to check if the resolution is ok, isn't it? Would you mind giving a shot to my updated code? maybe we can figure something else out and close this!
I really hope I'm only missing some color settings and someone can point out some error(s) or a stupid register setting because it looks to me I'm quite there but I can't grasp the last handhold.
You all can find the updated code on the usual repo on github!
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discussed below..
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me either .. yet
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the 16 bit data is clocked out as 2 bytes, I think with your two schemes you are simply reversing the order of the 2 bytes.
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I realised after last post that you are leaving most of the registers in the default state and also using VGA mode, I am using QVGA, so setting pretty much all of the timing registers as I am using an LCD with that resolution to test with.
This makes a huge difference as the module is VGA resolution and the windowing becomes important to me but not for you so much. VGA is much much easier and almost nobody is using QVGA. The register settings I have found online in assorted codes are not ideal and still leave you with massive lag due to clocking out more pixels than are relevant each line.
the HSTART and HSTOP basically set the portion of the image output for which the HREF line is high. The registers can also be changed so that the pixel clock is only output when HREF is active.
See COM10[5] and COM12[7] with those two set you should only get a pixel clock when there is active data.
This I will use later but for now I need to get the window and clock registers correct. You could use them with your code as is though if they are not the register defaults ..
The clocking out of the image data across the array is controlled by all the various dividers and dividers of dividers and also the actual clock speed used ( I think ) all i know is that simply slowing the clock divider changes the image, so I think internally the clock divider is used for output only and the XCLK is used undivided on the image array. just be aware that changing the clock divider (register 0x11) needs to be done with some thought..