PCB Design Comments

Does anyone have any comments about my first pcb design? =) hope to learn from you guys!

PCB_PCB_Water Dispenser_2021-06-18 (3).pdf (78.6 KB)
Schematic_Water Dispenser_2021-06-18.pdf (80.2 KB)

Edit: Here's all the layers. I didnt realize i did not select the bottom layer. sorry.
PCB_PCB_Water Dispenser_2021-06-18 (9).pdf (80.5 KB)

330nF seems like a weird value for the input to your 12v regulator.
Why do have a via between two pads where there is less clearance for it?
The pcb picture is not complete
More later.

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My only minor comments would be…

On schematics, I try to have signal flow from left to right.
The button inputs are pull-down, whereas my preference is pull-up unless there’s a reason to do so.

Otherwise no glaring things at first glance.
:heavy_check_mark::rainbow::coffee:

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Doesn't seem weird if you read the applications section of the datasheet...

For the layout I only see the top copper so can't judge really.

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I personally don't like 'join the dots' schematics, much better to have lines to show the connections.

R8 should be between ground and the Nano output pin, not the MOSFET gate. As you have it R8 and R9 form a potential divider, reducing the drive voltage to the MOSEFT (admittedly by not much).

You have R10 as a pull up on the coin acceptor, use the Nano internal pull up resistors instead.

I don't see the point of C9, please explain why you think you need it.

10k might be OK for R1 and R2, but I'd go for something close to 4k.

14V seems an odd supply voltage, where is that coming from?

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Yes, I just copied the circuit on the data sheet =D

the reason why i pull down is because i think (i dont know if thats the actual case) that if you pull up say buttons, they normally are on so wouldnt they be drawing current normally and buttons on a pulldown configuration would be normally off so they wouldnt draw current? I could be wrong it's just what i think is the case. hehe

Hi, Perry!

I followed other circuits that drive motors with mosfets thats why i came to this configuration and when I was setting the tracks, I was following the blue lines I think they're called nets? I dont know deep electronics so thanks for this. Ill try to look up potential dividers. =)

Will the internal pullup resistor be enough to pull up a coin acceptor because I read somewhere that the internal pullup isnt strong enough.

On the previous PCB i had someone make for me, it had a relay driving the pump but did not use optocouplers between ground and the transistor that drives the relay so I think it sends noise to the nano because sometimes, after the pump shuts off, the interrupt in my code (the interrupt reads the coin impulses) gets triggered. We fixed it by putting a capacitor between gnd and D2 (coin interrupt pin) I wasnt sure a mosfet would behave the same way as the relay (noise) and i wasnt sure an optocoupler was necessary so i just put it there because "it worked" but i figure its unnecessary and the mosfet wouldnt send noise triggering an interrupt then would it?

so ~3k+ ohm resistors then? got it.

its actually 12-14V I'm planning on running it with a LiFePo4 battery pack in a 4s configuration which ranges around 13-14v at full charge.

follow up question regarding the power source though, would i be having a problem with the voltage output in L12V or the linear 12v regulator for the coin acceptor assuming i power the system on grid with a 12v 20A power supply?

As you have it where you put R8 makes hardly any difference, but the proper place is on the output pin, not the MOSFET gate. In some situations is matters, so best to get into the right habit.

As you have provided no information about the coin acceptor I can't help any more. Based on what I assume to be the case the internal pull up resistors should be OK. Seeing information about the coin acceptor and how you plan to wire it might change my opinion.

You should not be using interrupts for a coin acceptor, your code should be polling the input, however, here we are talking about your circuit, not your code, so that's a discussion for elsewhere. You might need to deal with noise on the input and if you do the circuit you have might be OK, not sure, others might comment. I'm not happy with it though.

Yes, should be OK.

Then you can't use the linear regulator L12V to give you 12V as it needs more than 12V in to give 12V out. I have not looked up the specification of that regulator to see what the minimum input voltage is, you need to read the data sheet and find out. Your options are:
Used buck - boost converter, which will take a range of voltages from below 12V to above 12V and give 12V out.
Check the data sheet of the coin acceptor to see if it really needs exactly 12V, you might find it is perfectly OK with a range of voltages so does not need exactly 12V.

What makes you think you even need the 12V linear regulator if you plan to power the board with 12V? Of course you would not need it.

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Both configurations draw current. 3.3 picoamps. According to Atmega, the I/O pin as an input has an impedance of 100 megaohms, or 3.3e-8 Amps.

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I see. Thanks. Will do this.

It's a ch-926 coin acceptor. datasheet says it's 12v and consumes ~65mA of current i dont know how much it consumes when you insert a coin though. I'll try to breadboard and see internal pullup is ok.

Thank you!

Right! a boost buck would be perfect.

I'm not really sure about the power source yet because i plan to deploy one of these in the mountains where im from to provide drinking water there and one in town where theres electricity thats why I thought having regulators/buck would be a safer option in case i want to use a LiFePo4 battery pack but i realized i would have a problem if i use 12v power supply.

i think i have 2 options:

  1. design one specific for the LiFePo4 pack (with the regulators) and one for on grid setup (without regulators) or...

  2. go with the with a "without regulator" design and just use an inverter to power a 12v power supply if i use a battery pack.

Thanks for helping me realize this =D

Ok. Thank you!

Would there be a difference if i choose either pull up or pull down? because other than the reason i mentioned before about current draw, it also feels natural for me to write "if(digitalRead(button) == HIGH) { bla bla}" so pull down then do this only if its high.

If there is a difference between pull up and down and that pull up is more preferable, I would appreciate it if you point it out for me =D

I prefer to use the pull-up internal to the Atmega. Fewer parts on the board.

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Right. does it matter how many pins you pull up internally? is there some kind of limit as to how many before it cant handle it?

I've looked at it briefly, and while I would have drawn the schematic differently and also layed out the PCB differently (I probably would have shrunk it to about 1/3 it's current size), it'll likely work fine. The only thing I wouldn't be happy with is the lack of a fuse. It doesn't hurt to include a polyfuse between the 12v and the motor (or at the 12-14V input) and one after the 5V buck converter.

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never heard of a polyfuse. i will try to look that up. Thanks!

They're very convenient - they can save your board if something doesn't quite pan out, and you'll generally won't have to replace them.
One other thing you could consider is reverse polarity protection at the power input, but if you use poka-yoke plugs that can't be connected the wrong way, it would be overkill perhaps and just add complexity. There are lots of protections that you could consider and that you'll typically find on commercial products, but I assume you want to keep things simple for now.

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Just to a give a few comments, none of which are particularly critical, but that I certainly would have done differently to make things a bit more...well, elegant IMO and less likely to suffer from manufacturing defects (although commercial PCB manufacturers of course are capable of outright magic these days):

  • Prevent that via buried between two of the Nano's pins to be so close to those pads on both of its sides.
  • Remove one via connecting to R1; there are two now, but it's unnecessary.
  • Connections between R1-R2 but also R9-R8 might just as well have been straight lines; why make traces longer than they need to be?
  • Unnecessarily (IMO) narrow trace widths around R1 through R7.
  • Some traces running unnecessarily close to pads; e.g. at C9 and between R9 and the driver MOSFET.
  • The two traces between L1 and the B5V I would have just made parallel. Unless you're concerned with capacitive coupling, but that's unlikely to be an issue.
  • Place C1 close to the power jack.
  • Include a ceramic capacitor at the Vin of the B5V for filtering out HF noise.
  • There's an odd loop running around C4 towards the COIN_ACCEPT jack that only manages to increase the impedance of the GND connection of C4.
  • You do a pretty good job at keeping power traces wide, except for supplying the power to the Nano; why not make the trace from the + side of C2 to the Nano as wide as the others?
  • The 3V trace from the Nano to the RFID connector I would have made a bit wider to clearly indicate it as a power trace, and prevent it from running between those Nano pins on the north edge of the Nano.
  • Where are your GND vias? Your PCB design relies (at least the top layer) on a ground plane and I assume (...) that you have a copper pour connected to GND on both the top and bottom layers. If not, I'd recommend having them. The copper is there anyway; why have the lab etch it out if it doesn't hurt (at all!) to leave it on your PCB?
  • Given a two-layer design, I would have considered delegating for instance all power and ground traces to one layer and leave the signal traces on the top (or vice versa).
  • There's no copper pour around the big thermal pad of B5V although you have plenty of space for it.
  • Like I said, I would have shrunk this way down. There's vast areas of empty space on there, and the materials (FR4 board, copper etc.) are essentially wasted. Yes, it's probably just one PCB. But if we're designing without too much time pressure anyway (since most of us do this as a hobby), why not try to be considerate about it?

I could probably think of more, but keep in mind that these are mostly things that reflect my personal taste/preference, and for some of the issues above other people will recommend the exact opposite from what I say - you often balance one consideration against another.
And also remember what I said - none of these things are particularly problematic. Your layout will work (assuming the schematic is OK; didn't check it thoroughly), especially given the high-quality manufacturing standards of today.

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First of all, THANKS A LOT for taking the time to type all this. I appreciate this a lot.

I had the impression that straight lines counted as 90 degrees which every tutorial i watched said to never do. i realized a straight line is 180/360 degrees lol.

should i make them bigger? will do.

C9 = I thought when using capacitors, the closer the better. probably over did it lol.
R9 = liked the aesthetics of having the resistors close. also probably over did it. sorry.

to be honest i dont even know what "capacitive coupling" is and by "would have just made parallel what do you mean? I honestly just followed there the blue lines told me to connect.

ok. but like in the circuit diagram, c1 is from input and c2 is to output, since c1 should be near the input, does that mean c2 should be near the BV5? meaning a capacitor should be near the source its supposed to be filtering not the pin its supposed to be protecting like what you said i should do to c9?

i dont get it sorry. you dont have to explain though. will just have to research impedance might understand what you mean by then.

because i thought the nano eats up less current and making a too large trace would have a problem about induction or something?

yeah i was wondering how i would do that. maybe run it through the nano's butt? where there arent any pins? or do i have to go around the whole nano?

and by that do you mean like covering the whole pcb with copper to connect the grounds? i have it. just deleted it for the time being so the bottom traces show.

that was the original plan. probably did a poor job at placing the components thats why i was forced to go to the other layer.

will keep this in mind. again i cant thank you enough for taking the time to help me! THANK YOU SO MUCH!

You're welcome, and I'm glad you took my post the right way :slight_smile:
You said something about component placement, and while you actually did a pretty nice job IMO, it might have been even better. For instance, that remark about L1, I would have just put L1 just on top of B5V so the thing about the 'parallel traces' would have become a non issue. C could the go right next to/close to B5V, feeing up some space.

Yeah, there's some debate about 90-degree traces. In a PCB like yours, manufactured by a commercial lab, it's not really an issue. Best practice dictates indeed that we use 2x45 degrees instead of 1x90. But pads are already pretty big, so connections between traces and pads aren't considered to be angles. At least not by anyone I know.

Well, should...it will probably come out fine as it is, but yeah, I would have made all signal traces the same width and all power traces as well. Or perhaps have two widths of power traces; narrow ones for devices with small consumption and wider traces for devices with a larger power draw. Btw, there's no real issue with trace widths on your PCB in the sense of too high trace resistance.

It's not so much a placement thing, but the trance that runs from R9 along the gate pad of the MOSFET is really close to that gate. Again, will likely come out fine on your PCB, but you've got plenty of space anyway.

Essentially two parallel traces will form a very low-value capacitor. Especially in high frequency circuits this can become a problem. Your PCB doesn't pose very strict requirements on this.

Capacitors don't protect anything; they're a buffer of charge, and as such, they also have the tendency to charge up, resulting in large peak currents, especially the big capacitors. You want to limit those peak currents as much as possible as they're a source of noise. So generally speaking, people tend to put these buffer capacitors close to the source from which they get their energy, but decoupling capacitors (that form tiny local buffers and filter out line noise from or into a device) as close to the device as possible. So that's why you often see e.g. a 47uF electrolytic somewhere close to a power jack, but lots of small 100nF caps right at the pins of devices.

Let me clarify a bit: the trace that loops around C4 basically cuts through the top layer ground plane, so the connection between the GND pad of C4 and circuit GND is on the right hand side, which is narrower than the huge space you have on the left. Narrower = higher resistance, and impedance is the AC equivalent of resistance (to put it simply). It's an immaterial issue because either side will be plenty low impedance for what's happening in your circuit, but you know, see if we can do the best job we can, right?

The wider a trace, the less problematic any kind of interference is, in general (I'm sure there are exceptions, but let's stick to the general principle). As a trace becomes narrower, its resistance rises, together with parasitic capacitances this can form an RC circuit which can become an oscillator if active elements are present (usually the case these days) and/or result in poor transients. So in general, you want to keep trace resistance as close to 0 as possible.

There are trace width vs. resistance calculators online; if you try one out for your circuit, you'll see that again, this is not really a big issue.

For example; either could work. It will work as it is too, but I would probably run it along the left hand side of the Nano, underneath its USB connector. There are probably dozens of variants we could think of.

Yes, I assumed that. Same for the bottom, right? You can fill that one as well. But then you will have to throw in some vias between the top copper layer and the bottom copper layer. OK, the connectors and GND pins of the Nano will also act as vias, but good practice dictates that you want to keep resistance between ground planes as close to zero as possible. The last thing you want is a ground loop.
Btw, there are sometimes considerations to not have a ground plane in some place, which usually have to do with capacitance between traces on one side and the ground plane on the other. But for all intents and purposes, ground planes are our friends :wink: