You're welcome, and I'm glad you took my post the right way 
You said something about component placement, and while you actually did a pretty nice job IMO, it might have been even better. For instance, that remark about L1, I would have just put L1 just on top of B5V so the thing about the 'parallel traces' would have become a non issue. C could the go right next to/close to B5V, feeing up some space.
Yeah, there's some debate about 90-degree traces. In a PCB like yours, manufactured by a commercial lab, it's not really an issue. Best practice dictates indeed that we use 2x45 degrees instead of 1x90. But pads are already pretty big, so connections between traces and pads aren't considered to be angles. At least not by anyone I know.
Well, should...it will probably come out fine as it is, but yeah, I would have made all signal traces the same width and all power traces as well. Or perhaps have two widths of power traces; narrow ones for devices with small consumption and wider traces for devices with a larger power draw. Btw, there's no real issue with trace widths on your PCB in the sense of too high trace resistance.
It's not so much a placement thing, but the trance that runs from R9 along the gate pad of the MOSFET is really close to that gate. Again, will likely come out fine on your PCB, but you've got plenty of space anyway.
Essentially two parallel traces will form a very low-value capacitor. Especially in high frequency circuits this can become a problem. Your PCB doesn't pose very strict requirements on this.
Capacitors don't protect anything; they're a buffer of charge, and as such, they also have the tendency to charge up, resulting in large peak currents, especially the big capacitors. You want to limit those peak currents as much as possible as they're a source of noise. So generally speaking, people tend to put these buffer capacitors close to the source from which they get their energy, but decoupling capacitors (that form tiny local buffers and filter out line noise from or into a device) as close to the device as possible. So that's why you often see e.g. a 47uF electrolytic somewhere close to a power jack, but lots of small 100nF caps right at the pins of devices.
Let me clarify a bit: the trace that loops around C4 basically cuts through the top layer ground plane, so the connection between the GND pad of C4 and circuit GND is on the right hand side, which is narrower than the huge space you have on the left. Narrower = higher resistance, and impedance is the AC equivalent of resistance (to put it simply). It's an immaterial issue because either side will be plenty low impedance for what's happening in your circuit, but you know, see if we can do the best job we can, right?
The wider a trace, the less problematic any kind of interference is, in general (I'm sure there are exceptions, but let's stick to the general principle). As a trace becomes narrower, its resistance rises, together with parasitic capacitances this can form an RC circuit which can become an oscillator if active elements are present (usually the case these days) and/or result in poor transients. So in general, you want to keep trace resistance as close to 0 as possible.
There are trace width vs. resistance calculators online; if you try one out for your circuit, you'll see that again, this is not really a big issue.
For example; either could work. It will work as it is too, but I would probably run it along the left hand side of the Nano, underneath its USB connector. There are probably dozens of variants we could think of.
Yes, I assumed that. Same for the bottom, right? You can fill that one as well. But then you will have to throw in some vias between the top copper layer and the bottom copper layer. OK, the connectors and GND pins of the Nano will also act as vias, but good practice dictates that you want to keep resistance between ground planes as close to zero as possible. The last thing you want is a ground loop.
Btw, there are sometimes considerations to not have a ground plane in some place, which usually have to do with capacitance between traces on one side and the ground plane on the other. But for all intents and purposes, ground planes are our friends 