 # piezo signal conditioning circuit

here's my attempt in making one of these circuits. i've just designed it on an electronic simulation program, so i wonder if it would work with piezos, or if i can do something to properly simulate their behavior. here it is: a brief description: - VS and RS represent the piezo - R1 and R2 set the op-amp gain (10 in this case) - R4 and C1 make a low-pass filter, that smooths the input - D1 is a BAT85 diode, and cuts out the negative parts of the signal - D2 is a 5.1V zener diode, that cut the signal at about 5V the op-amp is supplied with VE=gnd and VC=9V

to sum up, my questions are: will it work? how can i impove it? are my representation of the piezo right? what's their impedance?

thanks in advance and feel free to use it :)

Hi,

A piezo looks like a voltage source in series with a capacitor. For simulation purposes, I suggest you assume a value of around 1nF to 10nF, however this is just a guess because it depends on the piezo.

1. To use VE=gnd you need to use an op amp whose input common mode voltage includes ground. There are several op amps available that meet this requirement, e.g. LM324.

2. Capacitor C1 is much bigger than the likely source capacitance of the piezo so it will cause severe attenuation of the signal. I suggest you remove C1 completely. Use a resistor (R4) of 10K or more between the piezo and the op amp input to limit the current flowing into the op amp when you accidentally drop a hammer on the piezo.

3. You need a resistor (I'll call it R3) between the non-inverting input of the op amp and ground (or in parallel with the piezo), to supply the input bias current to the op amp and keep the non-inverting input near ground potential. The input bias current of the LM324 is -100nA max at 25C. So with R3=100K you get up to +10mv at the input, and with R3=1M you get up to 100mV at the input. To avoid this being multiplied by the gain of the op amp, choose R1 and R2 so that if you were to put them in parallel, the resulting resistance would be the same as R3, or as close as you can reasonable get. For example, R3=200K, R1=220K and R2=2.2M.

4. D1 is not needed if you are using the LM324, because it is capable of accepting up to 50mA negative input current.

5. Gain of a non-inverting amplifier is 1 + (R2/R1), so the gain in your example is 11 not 10.

6. Limiting the output voltage with a zener diode is safe but not very kind to the op amp (or the battery, if the device is to be battery powered) because most op amps can supply quite a large output current. I suggest you connect a resistor between the output of the op amp and D2. Alternatively, just connect a 10K or greater resistor between the op amp output and the Arduino input pin and omit D2. The resistor will limit the current into the Arduino pin to less than 0.5mA, which its input protection diode can handle.

1. D1 is not needed if you are using the LM324, because it is capable of accepting up to 50mA negative input current.

I agree with most of dc42's comments. If VC = 9V and you want to limit Vout to 5V, you can use a voltage divider instead, or else add an R between the opApp and D2 to limit current, as dc42 mentioned.

What I would do is use another zener in place of D1 to protect the opAmp input terminal from large voltage spikes out of the Pz.

hi and thanks for your help! i've applied the modifications you suggested me, but i noticed i wasn't able to simulate the circuit due to a "singular matrix" error. however, here's some thoughts: 1) i forgot to say i will use the LM324, also because it come in a convenient package of 4 op-amps :) 2) i've increased the value of R\$, but do i really need to remove C1? i would like to smooth the incoming signal non to get a series of pulses on the output 3) despite reading this point many times, i haven't understood 4) D1 removed :) 6) thanks for the advice, i've put a resistor between the output and the diode to limitate the current

following your advices and messing a bit with the circuit, i end up with this: as you can see, i put R4 to limitate the input current, i reduced the gain to about 6, i added the current limiting resistor to the output as well as a filtering capacitator. on the simulation everything looks fine, what you you think?

one more thing: as you can see in my latest picture, when the wave reach negative values it saturate the output driving it to almost the VC rail value. is looks weird, can someone explain me this?

1. You need a resistor in parallel with the piezo, or alternatively from pin 1 of the op amp to ground. See my previous email. Without this, the circuit won't work at all, the output will go to +5v after a short while and stay there. Your simulation is incorrect because you have simulated the piezo as a voltage source, instead of a voltage source in series with a capacitor.

2. The output of the op amp is saturating in a positive direction when the input is negative because you are simulating with a very large input signal, much larger than you are likely to get from the piezo unless you hit it.

dc42: 1. You need a resistor in parallel with the piezo, or alternatively from pin 1 of the op amp to ground. See my previous email. Without this, the circuit won't work at all, the output will go to +5v after a short while and stay there. Your simulation is incorrect because you have simulated the piezo as a voltage source, instead of a voltage source in series with a capacitor.

1. today i tried again and i got that unknown error (singular matrix): i tried putting and removing many components, but it seems that it comes out whenever i put that capacitor in series, that's why i couldn't simulate the piezo correctly, as you adviced me. Thanks again for the corrections, il'll put a resistor in parallel with the piezo. are 100k, 470k or 1M good values, or it has to be smaller? also, why is it needed?

dc42: unless you hit it

1. that's what i'll do :)

HCPUNK:

dc42: 1. You need a resistor in parallel with the piezo, or alternatively from pin 1 of the op amp to ground. See my previous email. Without this, the circuit won't work at all, the output will go to +5v after a short while and stay there. Your simulation is incorrect because you have simulated the piezo as a voltage source, instead of a voltage source in series with a capacitor.

1. today i tried again and i got that unknown error (singular matrix): i tried putting and removing many components, but it seems that it comes out whenever i put that capacitor in series, that's why i couldn't simulate the piezo correctly, as you adviced me. Thanks again for the corrections, il'll put a resistor in parallel with the piezo. are 100k, 470k or 1M good values, or it has to be smaller? also, why is it needed?

Each input of the LM324 op amp is the base of a PNP transistor, which draws an input current of around 50nA. So imagine that the op amp has an internal 100M ohm resistor between each input and V+. The piezo (which behaves like a capacitor) will slowly charge up to V+. Actually, it's not a simple as that because the input bias current depends on the difference in voltage between the two inputs, but you get the idea. The resistor provides a path to ground for the bias current and stops the capacitor charging up too much.

As you are planning to hit the piezo and don't require a great deal of sensitivity, 100K should do. A larger value would give better sensitivity at low frequencies.

HCPUNK:

dc42: unless you hit it

1. that's what i'll do :)

In that case, some additional protection for the op amp would be a good idea, to limit the maximum positive voltage input (the op amp itself clamps the maximum negative voltage at about -0.6v, with a 50mA current rating). One possibility is the zener diode that another poster suggested. Another is a diode from the non inverting input to +5v.

that's it! (finally) hope that everything's right, i know i haven't put the protection diode you were talking about because the piezo will be very insulated, with a few rubber and foam, so even with the strongest hit i shouldn't get a 150Vpp :)

a final thought: since the piezo capacitance is an unwanted feature (isn't it?), what if i put a cap in series to it in order to decrease its value? ex: piezo capacitance = 10nF If i put a 5nF cap in series, i'll end up with 1/((1/10nF)+(1/5nF)) = 3.3nF total capacitance, right?

1. Putting a capacitor in series with the piezo will make the signal smaller, not larger.

2. Ideally you should choose R3 and R4 so that the total resistance seen by each input of the op amp is the same. That way, the effects of input bias current cancel out, minimising the offset voltage at the output when there is no input. Currently, pin 2 sees 410K and pin 3 sees about 8K (10K in parallel with 33K). So you should increase R4 to about 1.6M and R3 to about 510K, aiming for R3*R4/(R3+R4) = R1+R2.

i was referring to the piezo capacitance value, without any idea of how it can shape the sgnal

however, this morningi had the chance to try the circuit and i have to admit that it works quite well, making my piezo signal longer (10ms at +5V instead of a pulse) and closed in the 0-5 volts range. one of those days i'm going to put everything on a pcb