Not directly Arduino related, but probably there are some folks around that know the answer to my problem.
I'm trying to put a QFN-36 package in a library. The centerpad needs to be connected to the ground layer, so I'd like to put a via in the middle of it, so that I can connect it to a groundplane at the other side of the board.
But I don't really get it to work without producing DRC errors. I'll describe what I have done:
-Place a center pad on the top layer.
-Click the 'info' button, then the center pad and uncheck the 'cream' and 'stop' layer.
-(as suggested as per the link above): draw two rectangles manually over the center pad, one on the 'tstop' and one on the 'tcream' layer.
-Manually put a via over it.
This however doesn't seem to work. Any suggestions?
Its been my experience that this isn't the greatest of practices. While it is acceptable if necessary, it is usually better to instead place the via right next to the pad, and connect it with a very short lead. Ideally, the lead will be slightly less wide than the pad as well if possible. This allows for slower heat transfer into the ground plane, making soldering easier. Also, I think I've seen that some board companies don't allow or charge extra for via-in-pad. If you are absolutely out of board space, then it is okay, but its not recommended. Keep in mind you can extend the via to be under the chip itself as well, so if it is in the way, you can move it around.
via in pad has never caused me problems with 2-layer board with several
vendors, but its risky practice with small components as the surface tension
effects can cause tombstoning if the pads aren't symmetrical. For production
you would best avoid it unless you'd tested the reliability of reflow soldering for
the board in a prototype run.
Thanks for the answers and my apologies for the late reply.
The chip I'm trying to design a good footprint to is the VUB300 which comes in a QFN36 package.
I've attached the recommended footprint according to the datasheet.
The center pad needs to be attached to GND, and I could make the other side of the chip a groundplane.
I don't think I've got enough space to put a via next to the center pad, with all the little pads around it.
Would the solution maybe be to shrink the center pad, leaving an open zone in the middle where I can place a via? If I understood correctly the problem usually is that you could accidentally solder the via and the center pad together, but for my purpose this is exactly what I'm trying to do in the first place.
Place one or several vias Named GND within the exposed pad area. Accept the Eagle DRC errors. Name the pad GND within your library symbol as well.
When you review the gerbers with the free viewer from viewplot.com or similar it will be correct.
See page 6 - the exposed pad is called a "thermal slug" so it really does wantto be connected to the ground plane for cooling. http://www.saelig.com/supplier/elan/ES431-VUB300%20Datasheet-v14.pdf
I'm not sure how to do this in Eagle, but in DipTrace it is easy. I do it very often to create a thermal path to the bottom of the board for better heat sinking. BTW, yo can get DipTrace for free if your making small boards (less than 300 pins).
Can you not just add the pad to the GND net then, as already suggested, connect it to the GND pin of the IC on the pattern?
You're all making it over-complicated.
EAGLE generates a DRC warning/error when you have a via within a pad, all for good reasons (that several people have mentioned) that aren't really very applicable to the large central pads on QFN packages. Just "approve" the error, document that/why you did so, and move on... (All these schemes for preventing the DRC error won't change the reasons that the DRC error exists!)
