Problem verified
I am also having the same problem, and have verified that the C3 is only working on GPIO-0 no matter which Pin you actually run an analogRead
from. I started digging into the ESP core libraries (ESP by Espressif Version 2.0.0) to see if I could figure out why, and I believe I may be onto something...
Theory
I believe the problem is that the hardware abstraction layer define in the "esp32-hal-gpio.c" file never defines the pins for the C3 to begin with. "esp32-hal-gpio.h defines the esp32_gpioMux[] with is an array of esp32_gpioMux_t that holds pin mapping data for learning GPIO-->Analog pin assignments (as well as other stuff), and the esp32_adc2gpio[] holds pin mapping data for learning Analog-->GPIO pin assignments. There are 2 #defines, one for the ESP32, and one for the ESP32S2, but never one for the ESP32C3. This holds true for both the esp32_gpioMux[] and the esp32_adc2gpio. I believe, if these arrays are filled out for the C3, this will start working?
In the "esp32-hal-gpio.h" file, there is a macro for getting pin info out of the platform called
digitalPinToAnalogChannel(pin)
. As the name suggests, you give it your GPIO pin number, and it returns the Analog channel tied to it. If there is no Analog channel mapped to this pin, it returns -1.
The Test
I have all three flavors of board, so I ran a very simple test using the digitalPinToAnalogChannel(pin)
on each platform to view all the pin mappings. Here is the code:
void setup() {
Serial.begin(115200);
#if defined ARDUINO_ESP32_DEV
Serial.println("ARDUINO_ESP32_DEV");
#elif defined ARDUINO_ESP32S2_DEV
Serial.println("ARDUINO_ESP32S2_DEV");
#elif defined ARDUINO_ESP32C3_DEV
Serial.println("ARDUINO_ESP32C3_DEV");
#endif
for (int i=0; i<40; i++) {
Serial.println("D pin to A chan: " + String(i) + "=" + String(digitalPinToAnalogChannel(i)));
}
}
void loop() {}
The output from this test app:
//-----------------------------------------------------------------------------------------
// ESP32 OUTPUT
//-----------------------------------------------------------------------------------------
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:1
load:0x3fff0030,len:1240
load:0x40078000,len:13012
load:0x40080400,len:3648
entry 0x400805f8
ARDUINO_ESP32_DEV
D pin to A chan: 0=11
D pin to A chan: 1=-1
D pin to A chan: 2=12
D pin to A chan: 3=-1
D pin to A chan: 4=10
D pin to A chan: 5=-1
D pin to A chan: 6=-1
D pin to A chan: 7=-1
D pin to A chan: 8=-1
D pin to A chan: 9=-1
D pin to A chan: 10=-1
D pin to A chan: 11=-1
D pin to A chan: 12=15
D pin to A chan: 13=14
D pin to A chan: 14=16
D pin to A chan: 15=13
D pin to A chan: 16=-1
D pin to A chan: 17=-1
D pin to A chan: 18=-1
D pin to A chan: 19=-1
D pin to A chan: 20=-1
D pin to A chan: 21=-1
D pin to A chan: 22=-1
D pin to A chan: 23=-1
D pin to A chan: 24=-1
D pin to A chan: 25=18
D pin to A chan: 26=19
D pin to A chan: 27=17
D pin to A chan: 28=-1
D pin to A chan: 29=-1
D pin to A chan: 30=-1
D pin to A chan: 31=-1
D pin to A chan: 32=4
D pin to A chan: 33=5
D pin to A chan: 34=6
D pin to A chan: 35=7
D pin to A chan: 36=0
D pin to A chan: 37=1
D pin to A chan: 38=2
D pin to A chan: 39=3
//-----------------------------------------------------------------------------------------
// ESP32-S2 OUTPUT
//-----------------------------------------------------------------------------------------
ESP-ROM:esp32s2-rc4-20191025
Build:Oct 25 2019
rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3ffe6100,len:0x498
load:0x4004c000,len:0xa88
load:0x40050000,len:0x25a8
entry 0x4004c19c
ARDUINO_ESP32S2_DEV
D pin to A chan: 0=-1
D pin to A chan: 1=0
D pin to A chan: 2=1
D pin to A chan: 3=2
D pin to A chan: 4=3
D pin to A chan: 5=4
D pin to A chan: 6=5
D pin to A chan: 7=6
D pin to A chan: 8=7
D pin to A chan: 9=8
D pin to A chan: 10=9
D pin to A chan: 11=10
D pin to A chan: 12=11
D pin to A chan: 13=12
D pin to A chan: 14=13
D pin to A chan: 15=14
D pin to A chan: 16=15
D pin to A chan: 17=16
D pin to A chan: 18=17
D pin to A chan: 19=18
D pin to A chan: 20=19
D pin to A chan: 21=-1
D pin to A chan: 22=-1
D pin to A chan: 23=-1
D pin to A chan: 24=-1
D pin to A chan: 25=-1
D pin to A chan: 26=-1
D pin to A chan: 27=-1
D pin to A chan: 28=-1
D pin to A chan: 29=-1
D pin to A chan: 30=-1
D pin to A chan: 31=-1
D pin to A chan: 32=-1
D pin to A chan: 33=-1
D pin to A chan: 34=-1
D pin to A chan: 35=-1
D pin to A chan: 36=-1
D pin to A chan: 37=-1
D pin to A chan: 38=-1
D pin to A chan: 39=-1
//-----------------------------------------------------------------------------------------
// ESP32-C3 OUTPUT
//-----------------------------------------------------------------------------------------
ESP-ROM:esp32c3-api1-20210207
Build:Feb 7 2021
rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd6100,len:0x1428
load:0x403ce000,len:0xc04
load:0x403d0000,len:0x292c
SHA-256 comparison failed:
Calculated: 9f7363434bc7a1a2434ba3062500fa10b9fce5bb859899ee0424321b4ddaf742
Expected: 9b18b42e3e8e407f5e7b13f26c80172eda36d674c584e818f50843c766ebde69
Attempting to boot anyway...
entry 0x403ce000
I (48) boot: ESP-IDF v4.4-dev-2313-gc69f0ec32 2nd stage bootloader
I (49) boot: compile time 12:10:14
I (49) boot: chip revision: 3
I (49) boot_comm: chip revision: 3, min. bootloader chip revision: 0
I (55) qio_mode: Enabling default flash chip QIO
I (59) boot.esp32c3: SPI Speed : 80MHz
I (63) boot.esp32c3: SPI Mode : QIO
I (67) boot.esp32c3: SPI Flash Size : 4MB
I (71) boot: Enabling RNG early entropy source...
I (75) boot: Partition Table:
I (78) boot: ## Label Usage Type ST Offset Length
I (84) boot: 0 nvs WiFi data 01 02 00009000 00005000
I (91) boot: 1 otadata OTA data 01 00 0000e000 00002000
I (97) boot: 2 app0 OTA app 00 10 00010000 00140000
I (104) boot: 3 app1 OTA app 00 11 00150000 00140000
I (110) boot: 4 spiffs Unknown data 01 82 00290000 00170000
I (117) boot: End of partition table
I (120) boot_comm: chip revision: 3, min. application chip revision: 0
I (126) esp_image: segment 0: paddr=00010020 vaddr=3c030020 size=08898h ( 34968) map
I (139) esp_image: segment 1: paddr=000188c0 vaddr=3fc8b400 size=014b4h ( 5300) load
I (142) esp_image: segment 2: paddr=00019d7c vaddr=40380000 size=0629ch ( 25244) load
I (153) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=22498h (140440) map
I (176) esp_image: segment 4: paddr=000424c0 vaddr=4038629c size=04fe4h ( 20452) load
I (180) esp_image: segment 5: paddr=000474ac vaddr=50000000 size=00010h ( 16) load
I (183) boot: Loaded app from partition at offset 0x10000
I (185) boot: Disabling RNG early entropy source...
ARDUINO_ESP32C3_DEV
D pin to A chan: 0=0
D pin to A chan: 1=0
D pin to A chan: 2=0
D pin to A chan: 3=0
D pin to A chan: 4=0
D pin to A chan: 5=0
D pin to A chan: 6=0
D pin to A chan: 7=0
D pin to A chan: 8=0
D pin to A chan: 9=0
D pin to A chan: 10=0
D pin to A chan: 11=0
D pin to A chan: 12=0
D pin to A chan: 13=0
D pin to A chan: 14=0
D pin to A chan: 15=0
D pin to A chan: 16=0
D pin to A chan: 17=0
D pin to A chan: 18=0
D pin to A chan: 19=0
D pin to A chan: 20=0
D pin to A chan: 21=0
D pin to A chan: 22=-1
D pin to A chan: 23=-1
D pin to A chan: 24=-1
D pin to A chan: 25=-1
D pin to A chan: 26=-1
D pin to A chan: 27=-1
D pin to A chan: 28=-1
D pin to A chan: 29=-1
D pin to A chan: 30=-1
D pin to A chan: 31=-1
D pin to A chan: 32=-1
D pin to A chan: 33=-1
D pin to A chan: 34=-1
D pin to A chan: 35=-1
D pin to A chan: 36=-1
D pin to A chan: 37=-1
D pin to A chan: 38=-1
D pin to A chan: 39=-1
The Conclusion???
I really looks like the C3 just doesn't have it's GPIO/ADC pins mapped. The first 22 GPIOs point to Analog channel 0. And this A/D channel does indeed work as expected. Unfortunately, I'm not qualified to try and make these defines myself, and hope the community and/or Espressif can chime in and prove/disprove my findings and fix the C3 so we can use all 5 channels that are available on the Devkit.