Reading NRF24L01 status

Please bear with me because I only have limited understanding of what I'm doing and I'm trying to puzzle it out on my own.

I'm using NRF24l01 modules with Arduino pro mini clones attached.

For reasons I've described in other threads, I can't use the RF24 library, so am having to work at a more basic level, reading and writing directly to the NRF24L01 registers, which is currently just beyond my understanding

My immediate problem is how to get to the equivalent of if (radio.available()) - that is to say, I want the main part of the receiver code to execute only when a packet has arrived and to wait doing nothing until then.

It looks to me as though the FIFO_STATUS register is the place to look. According to the data sheet, in the condition I describe, bit 4 should be set (signifying that the tx buffer is empty) and bit I should also be set, meaning that the rx buffer is full. So - is it enough just to check that the decimal value of the register is 18?

eg can I do this:

while (SPI_Read(FIFO_STATUS)!=18);
if (SPI_Read(FIFO_STATUS)==18)
{do the rest of the code}

You don't want to know when the rx buffer is full, but when it is not empty.

This information (as well as the pipe the oldest packet was received on) is available in the status register.

Pretty obvious place to look for such information, don't you think?

robertjenkins:
For reasons I've described in other threads, I can't use the RF24 library,

That is only true for the transmitters and not for the receiver IIRC.

But even if you really could not use it, you could still have a look at its available() implementation.

while  (SPI_Read(FIFO_STATUS)!=18);
if (SPI_Read(FIFO_STATUS)==18)

You should never program blocking, the if is redundant. Overall pretty lame code.

Ah, I managed to confuse myself between the two registers, sorry.
So looking at the STATUS register, it appears that when bits 1 2 and 3 are set, the FIFO buffer should be empty?
(Bear in mind YMMV when it comes to obviousness. I did say I was at the edge of my understanding).

(Yes maybe I should have stuck to the library for the receivers but I thought it would be easier to have the two bits of code mirroring each other)

robertjenkins:
Ah, I managed to confuse myself between the two registers, sorry.
So looking at the STATUS register, it appears that when bits 1 2 and 3 are set, the FIFO buffer should be empty?

What does the implementation of available() tell you? Does it use FIFO flags?

This is what the RF24 library has to say about available(). I do not understand it but it refers to FIFO_STATUS which I think is why I was first looking there.

bool RF24::available(void)
{
  return available(NULL);
    return available(NULL);
}

/****************************************************************************/

bool RF24::available(uint8_t* pipe_num)
{
  if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){

    // If the caller wants the pipe number, include that
    if ( pipe_num ){
    uint8_t status = get_status();
      *pipe_num = ( status >> RX_P_NO ) & 0x07;
    }
    return 1;
  }

    if (! (read_register(FIFO_STATUS) & _BV(RX_EMPTY))) {

        // If the caller wants the pipe number, include that
        if (pipe_num) {
            uint8_t status = get_status();
            *pipe_num = (status >> RX_P_NO) & 0x07;
        }
        return 1;
    }

  return 0;
    return 0;


}

Apart from this, according to the datasheet there is a bit 6 of STATUS which is called RX_DR, data ready RX FIFO interrupt. This is "asserted when new data arrives RX FIFO. Write 1 to clear bit"

So maybe my while() statement should do nothing while RX_DR is not set, then do something as soon as RX_DR is set, then clear RX_DR by writing 1 to it (seems odd, but that's what it says), then back to the start again?

You should not use a while, at least not without a timeout IMHO.

I use the pipe number to detect a packet in the RX fifo, but the fifo status works obviously likewise.

I encountered some anomalies with the RX_DR bit in the context of ack-payload (it was delayed),
clearing the bit is only necessary if you want to use interrupts.