If it's that tight you'll have to get creative.
Any form of multi-master needs arbitration and without extra hardware that will take time and get complicated.
The SPI hardware is really just a fancy shift register.
To use SS or any pin as an interrupt or input to tell the slaves (sorry I have to think multiple slaves and one master) to load the data will I think be too slow.
I'm thinking the other way around, the slaves load the data into the SPI register unless told not to.
Use a pin as a load enable (we'll call it EN), ie during the brief inter-ADC reading period the slaves load 8 bits of data into the SPDR reg unless EN is high, in which case the reading may be discarded or not depending on if you really need every one.
So on the slave chips the code is like this
read ADC
if EN == LOW
write value to SPDR
All slaves are daisy chained so the master does the following
raise EN
for (n = 0; n < number_of_slaves; n++)
SPI.transfer
lower EN
This of course means that for ( slaves * 8 ) bit times the slaves are effectively disabled from updating their ADC reading. This may or may not matter depending on the number of slaves and the importance of getting every reading.
You can maybe speed this up by reading say 8 slaves in parallel. Run all the slave MISO pins to digital inputs of the master. So assuming <= 8 slaves
raise EN
pulse clock pin
bits0 = PORTD;
pulse clock pin
bits1 = PORTD;
pulse clock pin
bits2 = PORTD;
pulse clock pin
bits3 = PORTD;
pulse clock pin
bits4 = PORTD;
pulse clock pin
bits5 = PORTD;
pulse clock pin
bits6 = PORTD;
pulse clock pin
bits7 = PORTD;
lower EN
It looks bad but might be faster than getting 64 bits bytes via the SPI. Of course the bytes have to be reconstructed but that can be done later.
If you need all 10 ADC bits then I guess the above has to be duplicated (but only two more pulses needed) and the slaves are once again disabled for the duration of the transfer.
If you absolutely can't afford to lose a reading and need 10 bits I think you'll have to throw hardware at the problem.
Rob
