Hi there, there is this shield designed to manage several incremental encoders. (old post presenting this shield here: LS7366RSH - 6 Channel LS7366R 32-Bit Quadrature Counter Development Shield).
It's using the LS7366R chip, which is a 32 bit counter, the datasheet can be found here: https://lsicsi.com/wp-content/uploads/2021/06/LS7366R.pdf
I would like some help in understanding the implementation of the chip on the board: full shematic here
What is the point of these components and how were they chosed? I think i got it right fort the first two elements from this list, but then i will need your help:
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C19 is i believe a bypass capacitor: between VSS and VCC.
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R25, R28, R22 and R34 seem to be 20kOhm pull-up resistors, to keep the pin input in a non ambiguous state at all times.
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C16, at the output of the clock signal (which is given by the master MCU on the board).
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resistor R16 of 33 Ohm on the clock input.
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the resistors of 100 Ohm: R56, R59, R62, R72.
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the capacitors of 10pF: C40, C43, C46, C52.
I must add that the pins A and B, will receive the quadrature signal from the incremental encoder. and the pin Z will receive the index signal from the incremental encoder.
I also stress the following point: in the red circle at the bottom right corner of the screenshot, there should be written GND everywhere and not +5V. The +5V comes from the chip just under that i blanked for the sake of clarity.
thanks for your time reading,
charlie armstrong