I need some help currently, i want to control 2 train signals (one of the signals uses an exta yellow and green signal, so it uses 5 outputs)
I got some advice and was told to use a &= operator to help clear only the appropriate bit that is being uses for that one signal. However some of the switch cases are not properly bring cleared, leading to some bits staying on. Below is the code:
// Pin assignments
const int dataPin = 2; // Connect to DS (Pin 14) on the 74HC595
const int latchPin = 3; // Connect to ST_CP (Pin 12) on the 74HC595
const int clockPin = 4; // Connect to SH_CP (Pin 11) on the 74HC595
// Timing intervals
const unsigned long intervalSignal1 = 1000; // 1000 ms for Signal 1
const unsigned long intervalSignal2 = 579; // 579 ms for Signal 2
// State variables for timing and state tracking
unsigned long previousMillisSignal1 = 0;
unsigned long previousMillisSignal2 = 0;
int stateSignal1 = 0;
int stateSignal2 = 0;
// Global state of all outputs
byte currentState = B00000000;
void setup() {
// Set pin modes
pinMode(dataPin, OUTPUT);
pinMode(latchPin, OUTPUT);
pinMode(clockPin, OUTPUT);
// Initialize the shift register with all outputs off
updateShiftRegister();
}
void loop() {
// Check the time for Signal 1
if (millis() - previousMillisSignal1 >= intervalSignal1) {
previousMillisSignal1 = millis(); // Reset the time
updateSignal1();
}
// Check the time for Signal 2
if (millis() - previousMillisSignal2 >= intervalSignal2) {
previousMillisSignal2 = millis(); // Reset the time
updateSignal2();
}
}
void updateSignal1() {
// Cycle through the states for Signal 1
switch (stateSignal1) {
case 0:
currentState &= B00001111; // Clear Signal 1 bits (Q0, Q1, Q2, Q4, Q6)
currentState |= B00000100; // Set Q2
break;
case 1:
currentState &= B00001111; // Clear Signal 1 bits
currentState |= B01010000; // Set Q4 + Q6
break;
case 2:
currentState &= B00001111; // Clear Signal 1 bits
currentState |= B00010010; // Set Q1 + Q4
break;
case 3:
currentState &= B00001111; // Clear Signal 1 bits
currentState |= B00000011; // Set Q0 + Q1
break;
}
stateSignal1 = (stateSignal1 + 1) % 4; // Cycle through 4 states
updateShiftRegister(); // Update the shift register with the new state
}
void updateSignal2() {
// Cycle through the states for Signal 2
switch (stateSignal2) {
case 0:
currentState &= B00001111; // Clear Signal 2 bits (Q3, Q5, Q7)
currentState |= B10000000; // Set Q7
break;
case 1:
currentState &= B00001111; // Clear Signal 2 bits
currentState |= B00100000; // Set Q5
break;
case 2:
currentState &= B00001111; // Clear Signal 2 bits
currentState |= B00001000; // Set Q3
break;
}
stateSignal2 = (stateSignal2 + 1) % 3; // Cycle through 3 states
updateShiftRegister(); // Update the shift register with the new state
}
void updateShiftRegister() {
// Use latch to update shift register output
digitalWrite(latchPin, LOW);
shiftOut(dataPin, clockPin, MSBFIRST, currentState);
digitalWrite(latchPin, HIGH);
}
(Q3, Q5, Q7 are signal 2, rest are for signal)
What changes neeed to be made so the only the appropriate bits are cleared and masked? Thank you