27C256 EPROM Emulator using SRAM and ATTINY3216

I'm starting to get back into playing around with some microprocessors of my youth - Z80, 8085 and 68000. I've got myself a little RC2014 setup using a Z80 processor board, serial & timer board, compactflash board and a breakout board to ease myself back into the saddle.

It took a bit of fiddling around to get the EPROM setup right. I actually used an EEPROM instead as I don't have a PROM eraser. The process needed several insertions and removals of the EEPROM for reprogramming.

That got me thinking that maybe I could build myself an EPROM emulator using a suitable SRAM chip, one of the ATTiny chips and an I/O expander. Maybe I could use the ATTiny and I/O expander to "program" the SRAM with my EPROM contents and then let the target system boot as it were.

I came up with the following schematic as a bit of a concept design:


I figured I could program the ATTiny via UPDI and upload (or even download) SRAM contents via the UART. The target system would have to be held in a reset state whilst this was happening.

The bit I'm stuck on is that it's likely that some if not all signals will still be driven to a 0 or a 1 from discrete TTL chips and/or GALs etc whilst the target processor is held in reset.

Is it possible to somehow "over-ride" these logic levels without introducing the complexity of additional ICs - I'd like to use SOIC devices and maybe even stay close to the footprint of a 27C256.

My initial thought was to have something like this on each pin:
input_pin
In the hope that the ATTiny and I/O expander would then be able to "over-ride" the signals coming from the target board.

Once programming had completed, I would then set the ATTiny and I/O expander pins to inputs and then bring the target processor out of RESET and let it loose on the code stored in the SRAM.

Any help or suggestions appreciated.

With a 100R resistor a current up to 50mA will flow what can damage many chips. 1k were safer.

I'd try to implement a boot loader on the target controller that writes initial data to the SRAM. A single switch could swap the address range or CS of the ROM and SRAM.

I figured that there would be some obvious gotcha like that.

Having slept on it, I think I might have a look at a 2 board design. Lower board plugs into the actual EPROM socket and has some octal bus transceivers on it that I can use to isolate the target hardware from the upper board that contains the SRAM chip and maybe switch to a 4809 micro to handle the programming of the SRAM.

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