74HC165 daisy chain bit order?

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1

Hi, in which order bites comes out from a 74HC165 daisy chain?

I guess D0 from the first chip (connected to the MCU) comes out first and the D7 of the last chip comes out last. I guess this is how it should be. (probably wrong, see EDIT)
Am I correct?

It spits out D0->D1->D2... and DS acts like a non latching "D8"? (probably wrong, see EDIT)

Please see the diagram.

445×1438 31.1 KB

Also do I understand correctly that ~CE (CLK INH)... clock inhibit pin is useless when there is no central CLK signal? When I generate CLK with MCU only when needed, can I just ground the ~CE pin?

Thanks.

EDIT:
WOW, everything I said was wrong I guess.

From what I see in the datasheet it looks the other way:

863×300 68.7 KB

So D7/H is first out? And the DS/SER is like a "D-1"?

D7->... -> D0 -> D7 (second chip) -> ... -> D0 (second chip)...

2

There is a central CLK signal in your design, "IN_CLK". If there isn't, there should be.

3

IN_CLK is "clock signal for input shift registers" it is dedicated only for these three 74HC165. These will always work in sync.

4

Okay, well I guess someone somewhere has a board with a boatload of 165's, but I think the clock inhibit pin is more general purpose than for selecting one or several SR's out of a set. A finer point, though... yes you can ground CLK INH.

Since they are cascaded, your "IN_SHIFT" can also be combined.

5

All IN_SHIFT are connected.
All IN_CLK are connected.
All IN_CLK_~EN are connected to GND - it makes sense it goes to the same NOR gate as CLK.

Now I just need to confirm the serial output order.

6

You labelled it correctly, don't worry. You can't really fail because it's either D0..D7->D0...D7k-> or D7...D0->D7...D0->

It's really just a matter of names if you have the SR's wired correctly.

7

I know it will work one way or the other. Unfortunately I need to make a PCB and if I get this wrong I will have to make some SW correction, lookup table - I don't like SW corrections for a bad HW.

Can someone please confirm that the first out is D7?
D7 (first chip) ->... -> D0 (first chip) -> D7 (second chip) -> ... -> D0 (second chip)...

8

I'd say that based on the data sheet extract in post #1 , it is this :

|chip1||chip2||chip3| out
ABCDEFGABCDEFGABCDEFG 
111010110100000100110
 11101011010000010011 0
  1110101101000001001 1
   111010110100000100 1  
    11101011010000010 0
etc. 
etc.

How are you going to read the serial stream ? with shiftIn() ? If so, you have something else to consider and that is whether you read it in MSB first or LSB first (most/least significant bit).

If it is important, then try it first. I'd simply correct it in software if it turns out to be different.

9

By "chip1" you mean "first chip" from my circuit diagram?
Because if so it does not make sense.
Data should propagate only towards the MCU.

chip3 - > chip 2 -> chip1 -> MCU

It make sense only if by "chip3" you mean "first chip" closest to the MCU.

shiftIn() is only 8bit, I will write custom routine.

10

I didn't compare it with your diagram but it would be:
your Last Chip is chip 1 in post #8
your middle Chip is chip 2 in post #8
your first Chip is chip 3 in post #8

You could call shiftIn() 3 times consecutively. There you can reverse the bit order within a byte if required. Reversing the byte order is also a simple change. So the risks of a big error are quite low.

11

Perfect, thanks!

12

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