It's an 8-bit processor, and I am not familiar with any advantages to be gained by moving alignments to word boundaries. So I wouldn't bother with the pack pragma.
I'm not implying anything about bytes or words. What I wanted to know is if the arduino runs on a 1 byte boundary. As in class data members will not be padded to correctly align them.
I have no problem, I need to know this to construct my code properly, it shouldn't be such an 'unmentionable' topic as it seems here.
lets just whip up an example
struct mystruct{
int a;
char b;
bool c;
};
This structure under 1-byte alignment would occupy 5 bytes assuming int is 16-bit.
Under 2-byte alignment. this structure would occupy 6 bytes as a padding byte would be inserted after 'char b' to ensure 'bool c' starts on a 2-byte boundary.
Well thats a simple error on my part, I assumed also that bool is two bytes like many other c++ implementations. Exactly my point of asking this question... So I don't have to assume things.
one major player in alignment is backwards compatibility. Found in the Win API transition from 16-bit to 32-bit then to 64-bit.
structures passing data to functions have been extended and these are required to be in certain alignments to be usable by both old and new code. by using the structure size, a version type can be established. With no default alignment the structures could vary in size resulting in the wrong execution of code.
I know windows and any other implementation is unrelated to what could be in the arduino, this is just an example.
As your sketch output was 4 bytes, I'm still assuming its a 1 byte boundary, the char and bool still sit side by side in a 2-byte alignment. I guess I'll do up my own sketch with an extra few variables to enforce padding if it exists.
Thanks for the input anyway. I still want to find a definitive answer as knowing it will benefit me in the future. I have only just started with arduino 4 weeks ago so I'm simply trying to understand it as much as possible.
Interpretting the output it does indeed look like an 8bit processor, with 2 byte pointers and 4 byte pointer to member functions.
I was curious if I could squeeze some compiler-generated padding out of my datastructures by reordering the members, but it looks like there isn't much to do. (Hmmm... except squash booleans into bits of a single field.)
drewfish:
I was curious if I could squeeze some compiler-generated padding out of my datastructures by reordering the members, but it looks like there isn't much to do. (Hmmm... except squash booleans into bits of a single field.)
Hehe... yeah I agree that macros such as I posted here are a really bad idea for any code that is intended to be maintained. The code I posted wasn't intended to be maintained, but just a quick one-off to gather real-world info on data type sizes and alignments. Sorry, I won't inflict my cleaver macros on y'all again
(BTW I think simple macros do have their place. For example the Arduino API has quite a few.)
drewfish:
(BTW I think simple macros do have their place. For example the Arduino API has quite a few.)
I Agree, however rendering valuable names in every namespace unusable was a terrible choice ( Arduino API ).
I'm sure somebody may want a class with members called min, or max.
Or at least the possibility of overloading them ( if they were a real function ).
I had a problem today on the Due... after hours tracked it down to a struct. The last field was a "byte" and instead of the size being 21... it was 24.
As it was a header for a file... when I read it in it was reading 3 too many and after that... all hell broke loose.
I will give a very good reason for alignment
I am currently looking at this very issue because I need to pass binary data to an STM32 from an Arduino Nano over i2c interface, there is a problem with different size records due to the crazy way word is defined in the C language
I also have to pass this data via UDP to a Pascal program and I spent the day massaging records to get the mess to align
It took mere seconds in Pascal to ensure a packed record
On small devices with a mere 20k of ram, size matters