Could someone please explain me the difference between VDD and VDDIO/VIO.
For example, I have the flash (S25FL128S) with Core Supply Voltage: 2.7V to 3.6V and I/O Supply Voltage: 1.65V to 3.6V, or a IMU MPU9250 with VDD supply voltage range of 2.4 – 3.6V and VDDIO range of 1.71 to VDD.
I understood the VDD is the main supply while VDDIO is separate supply for the digital interfaces, but what does that mean exactly.
If I power these devices using a single supply, say, 2.2 V, which is lower than the min main supply but higher than the min IO supply, am I still able to operate with these devices?
It's bad practice to make assumptions about electronic device specs.
That's what the datasheets are for.
while VDDIO is separate supply for the digital interfaces
Not quite.
It's a reference voltage for auxiliary I2C devices, (an auxiliary I2C bus)
See page 6 and page 37
Serial Interface Considerations
8.1 MPU-9250 Supported Interfaces
The MPU-9250 supports I2C communications on both its primary (microprocessor) serial interface and its
auxiliary interface.
The MPU-9250’s I/O logic levels are set to be VDDIO.
The figure below depicts a sample circuit of MPU-9250 with a third party sensor attached to the auxiliary I2C bus. It shows the relevant logic levels and voltage connections.
soleilsword:
Could someone please explain me the difference between VDD and VDDIO/VIO.
For example, I have the flash (S25FL128S) with Core Supply Voltage: 2.7V to 3.6V and I/O Supply Voltage: 1.65V to 3.6V, or a IMU MPU9250 with VDD supply voltage range of 2.4 – 3.6V and VDDIO range of 1.71 to VDD.
I understood the VDD is the main supply while VDDIO is separate supply for the digital interfaces, but what does that mean exactly.
It means the FETs driving the input/output pins are powered from VddIO, not Vdd, allowing the I/O voltage to be somewhat different from the core voltage.
Lower core voltage allows much faster internal logic. I/O pins need higher voltage to talk to other chips and to have decent noise-immunity.
The die for this chip will have an area round the edge holding the "pads", being the drivers and protection circuitry for each I/O pin. This area will have different transistor parameters from the core allowing higher voltage slower FETs. VddIO is routed to this area, Vdd is routed to the central core.
Modern CMOS processes can allow core logic speeds measured in GHz and 10's of GHz, whereas I/O pin limits are
about 500MHz (LVDS) or 100MHz (full swing) due to the stray capacitance and power limitations. Stray capacitance of signals inside the core is measured in femtofarads (fF), whereas pins have stray capacitances measured in picofarads, (pF), much larger. A core FET couldn't drive that kind of load at all.
soleilsword:
If I power these devices using a single supply, say, 2.2 V, which is lower than the min main supply but higher than the min IO supply, am I still able to operate with these devices?
For reliable operation both VDD and VDDIO have to be within their respective specified ranges. VDDIO should match the IO voltage range of the device to which it is connected.